Memory System Tester Using Test Pad Real Time Monitoring

1. A memory system tester comprising: connections to couple to a memory system interface to test a memory system, with the memory system tester being physically different from the memory system under test and the memory system interface detachable from the memory system; a test flow controller arranged to generate test signals to the memory system using the memory system interlace coupled externally to the memory system to couple to a controller of the memory system, the memory system having one or more memory devices coupled to the controller of the memory system by a bus of the memory system; and an analyzer coupled to the test flow controller with the analyzer arranged to couple to external test pads of a package platform for the memory system using an interface to the external test pads, with the interface to the external test pads being separate from the memory system interface and with the external test pads coupled to the bus of the memory system, such that the analyzer is operable to provide data to the test flow controller to conduct testing of the memory system using the memory system interface and the interface to the external test pads simultaneously, the data based on real time monitoring of the external test pads of the package platform.

2. The memory system tester of claim 1 , wherein the test flow controller and the analyzer are integrated together in a field programmable gate array system.

3. The memory system tester of claim 1 , wherein the test flow controller is arranged to control flow of testing of the memory system based on status of internal voltages of the memory system monitored by the analyzer at a number of the external test pads of the package platform at which the respective external test pads reflect the internal voltages of the memory system.

4. The memory system tester of claim 1 , wherein the test flow controller is arranged to generate memory commands to the controller of the memory system via the memory system interface and to control processing of execution of memory commands by the memory system.

5. The memory system tester of claim 4 , wherein, for a program command generated for testing, the test flow controller is arranged to stop programming the memory system in response to the data from the analyzer including a determination that programming errors in number have reached or exceeded a threshold for a number of errors allowed, the programming errors in number based on real time monitoring, by the analyzer using a number of the external test, pads, of the bus coupling the controller to the one or more memory devices of the memory system.

6. The memory system tester of claim 1 , wherein the memory system is a managed NAND system, the one or more memory devices are one or more NAND memory devices, the bus is a NAND bus, the memory system interface is a managed NAND interface, and the interface to the external test pads is a NAND interface.

7. The memory system tester of claim 6 , wherein the test flow controller and the analyzer are integrated together in a field programmable gate array system.

8. The memory system tester of claim 6 , wherein the test flow controller is arranged to control flow of testing of a NAND memory device of the managed NAND system and/or the managed NAND system, based on status of internal voltages of the NAND memory device and/or the managed NAND system, monitored by the analyzer at a number of the external test pads at which the respective external test pads reflect the internal voltages of the NAND memory device and/or the managed NAND system.

9. The memory system tester of claim 6 , wherein the analyzer is operable to communicate to the test flow controller that a NAND operation is in progress and the test flow controller is operable to conduct a power loss test during the NAND operation in progress in response to receiving communication that the NAND operation is in progress.

10. The memory system tester of claim 6 , wherein the memory system tester is operable to evaluate firmware of the managed NAND system by measurement of time associated with execution of a NAND operation from generation, by the test flow controller, of a command to perform the NAND operation and measurement of time associated with signals, corresponding to the execution of the command, on the NAND bus using a number of the external test pads coupled to the NAND bus with the managed NAND system coupled to the package platform.

11. The memory system tester of claim 6 , wherein the memory system tester is operable to provide test coverage of operations on a NAND memory device of the managed NAND system and/or measure wear-leveling of the NAND memory device from a monitoring of the NAND bus of the managed NAND system to check status of the NAND memory device directly.

12. The memory system tester of claim 6 , wherein the analyzer is structured as multiple NAND analyzers with each NAND analyzer arranged to access one NAND channel of multiple NAND channels of the NAND bus of the managed NAND system, the one NAND channel being different from channels accessed by other NAND analyzers of the multiple NAND analyzers, the access by each NAND analyzer arranged via test pads of the external test pads different from other external test pads used by the other NAND analyzers, with each NAND channel coupling one or more NAND dies to the controller of the managed NAND system.

13. The memory system tester of claim 6 , wherein the analyzer includes a log to hold commands and addresses associated with commands of NAND operations from monitoring of a number of the external test, pads coupled to the NAND bus with the managed NAND system coupled to the package platform.

14. The memory system tester of claim 13 , wherein the analyzer in conjunction with the test flow controller is operable to conduct debugging using the log.

15. The memory system tester of claim 6 , wherein the analyzer, using selected external test pads of the external test pads, in conjunction with the test flow controller is operable to generate a command to execute an operation in a NAND memory device of the managed NAND system, measure current in the managed NAND system, correlate the current with the operation that is ongoing in the NAND memory device, and produce a statistic with respect to peak current and status of the NAND memory device.

16. The memory system tester of claim 6 , wherein the analyzer, from monitoring by use of selected external test pads of the external test pads coupled to the NAND bus and in conjunction with the test flow controller, being operable to determine in real time when a number of NAND page programs or block erases is greater than a threshold for page programs or block erases.

17. The memory system tester of claim 6 , wherein the analyzer is operable to generate a communication to the test flow controller that a NAND operation is in progress, and the test flow controller is operable to conduct testing of NAND and controller power management during the NAND operation in progress, in response to reception of the communication that, the NAND operation is in progress, with the analyzer arranged to monitor internal voltages of the managed NAND system to conduct the testing in conjunction with the test flow controller.

18. A processor-implemented method comprising: testing a memory system using a memory system tester, with the memory system tester being physically different from the memory system under test and having connections coupled to a memory system interface to test the memory system, with the memory system interface detachable from the memory system, the memory system tester having a test flow controller and an analyzer, the testing including: generating a flow of test signals from the test flow controller to the memory system using the memory system interface coupled externally to the memory system to couple to a controller of the memory system, the memory system having one or more memory devices coupled to the controller of the memory system by a bus of the memory system; monitoring external test pads of a package platform for the memory system, using the analyzer coupled to the external test pads of the package platform via an interface to the external test pads, with the external test pads coupled to the bus of the memory system and with the analyzer coupled to the test flow controller as part of a memory, system tester, with the interface to the external test pads being separate from the memory system interface; providing data from the analyzer to the test flow controller, the data based on real time monitoring of the external test pads of the package platform; and using the data by the test flow controller to conduct the testing of the memory system using the memory system interface and the interface to the external test pads simultaneously, including controlling the flow of the test signals based on the data.

19. The processor-implemented method of claim 18 , wherein the test flow controller and the analyzer are integrated together in a field programmable gate array system.

20. The processor-implemented method of claim 18 , wherein the memory system is a managed NAND system, the one or more memory devices are one or more NAND memory devices, the bus is a NAND bus, the memory system interface is a managed NAND interface, and the interface to the external test pads is a NAND interface.

21. The processor-implemented method of claim 20 , wherein controlling the flow of the test signals includes controlling the flow based on status of internal voltages of the one or more NAND memory devices and/or the managed NAND system monitored by the analyzer at a number of the external test pads of the package platform at which the respective external test pads reflect the internal voltages of the NAND memory device and/or the managed NAND system.

22. The processor-implemented method of claim 20 , wherein the processor-implemented method includes: generating a communication from the analyzer to the test flow controller that a NAND operation is in progress; and conducting, from the test flow controller, a power loss test during the NAND operation in progress in response to the test flow controller receiving the communication that the NAND operation is in progress.

23. The processor-implemented method of claim 20 , wherein the processor-implemented method includes: measuring time associated with execution of a NAND operation from generation, by the test flow controller, of a command to perform the NAND operation; measuring time associated with signals, corresponding to the execution of the command, on the NAND bus of the managed NAND system using the analyzer monitoring a number of the external test pads of the package platform coupled to the NAND bus with the managed NAND system coupled to the package platform; and evaluating firmware of the managed NAND system using the measured time associated with execution of the NAND operation by the test flow controller and the measured time associated with signals on the NAND bus of the managed NAND system monitored by the analyzer.

24. A non-transitory machine-readable storage device storing instructions, that when executed by one or more processors, cause a machine to perform operations to: test a memory system using a memory system tester, with the memory system tester being physically different from the memory system under test and having connections coupled to a memory system interface to test the memory system, with the memory system interface detachable from the memory system, the memory system tester having a test flow controller and an analyzer, the testing including operations to: generate, by the test flow controller of the machine, a flow of test signals to a memory system using the memory system interface coupled externally to the memory system to couple to a controller of the memory system, the memory system having one or more memory devices coupled to the controller of the memory system by a bus of the memory system; monitor, by the analyzer of the machine, external test pads of a package platform for the memory system when the analyzer is coupled to the external test pads of the package platform via an interface to the external test pads, with the external test pads coupled to the bus of the memory system, with the analyzer coupled to the test flow controller as part of a memory system tester, with the interface to the external test pads being separate from the memory system interface; provide data from the analyzer to the test flow controller, the data based on real time monitoring of the external test pads of the package platform; and use the data, by the test flow controller, to conduct testing of the memory system using the memory system interface and the interface to the external test pads simultaneously, including control of the flow of the test signals based on the data.

25. The non-transitory machine-readable storage device of claim 24 , wherein the memory system is a managed NAND system, the one or more memory devices are one or more NAND memory devices, the bus is a NAND bus, the memory system interface is a managed NAND interface, and the interface to the external test pads is a NAND interface.

26. The non-transitory machine-readable storage device of claim 25 , wherein the operations include a determination, in real time, of an occurrence of a number of NAND page programs or block erases being greater than a threshold for page programs or block erases, by monitoring of selected external test pads of the external test pads of the package platform coupled to the NAND bus, in conjunction with control, by the test flow controller, of a flow of commands to the managed NAND system.

27. The non-transitory machine-readable storage device of claim 25 , wherein the operations include: maintenance of a log containing commands and addresses associated with the commands of NAND operations from monitoring of a number of the external test pads coupled to the NAND bus with the managed NAND system coupled to the package platform; and performance, by the analyzer in conjunction with the test flow controller, of debugging by use of data in the log.