Controller and Memory System Including the Same

1. A memory system comprising: a nonvolatile memory device; and a controller configured to control the nonvolatile memory device, wherein the controller is further configured to: receive a write command for storing write data, currently stored in at least one memory region among a plurality of memory regions in a host memory, in the nonvolatile memory device, generate a host memory map table by mapping virtual addresses to host memory physical addresses corresponding to the at least one memory region, and transmit the write data to the nonvolatile memory device from the host memory based on the host memory map table, wherein the controller identifies the at least one memory region in the host memory with reference to the host memory physical addresses.

2. The memory system of claim 1 , wherein the controller generates the host memory map table by mapping the virtual addresses to the host memory physical addresses corresponding to a plurality of sub memory regions within the at least one memory region, each of the plurality of sub memory regions having a set size.

3. The memory system of claim 2 , wherein the set size is a data size unit to be processed in the memory system.

4. The memory system of claim 2 , wherein the nonvolatile memory device includes: a memory cell array including a plurality of data storage regions; and a page buffer configured to temporarily store the transmitted write data, wherein the set size is a data size to be stored in the page buffer.

5. The memory system of claim 2 , wherein the controller generates the host memory map table by setting indexes to the host memory physical addresses and mapping the virtual addresses to the set indexes.

6. The memory system of claim 5 , wherein the indexes are offset values from the lowest host memory physical address among the host memory physical addresses.

7. The memory system of claim 2 , wherein the write command includes information of a size of the write data and the host memory physical addresses corresponding to the at least one memory region, and wherein the controller generates the host memory map table based on the information.

8. A controller which controls a nonvolatile memory device, the controller comprising: a first interface configured to perform data communication with a host; a second interface configured to perform data communication with the nonvolatile memory device; and a processor configured to control operations of the first and second interfaces, wherein the first interface receives, from the host, a write command for storing write data, which is currently stored in at least one among a plurality of memory regions in a host memory, wherein the processor generates access information corresponding to host memory physical addresses, which respectively correspond to a plurality of sub memory regions within the at least one memory region, each of the plurality of sub memory regions having a set size, in response to the received write command, and wherein the second interface transmits the write data to the nonvolatile memory device from the host memory based on the access information, wherein the controller identifies the sub memory regions in the host memory with reference to the host memory physical addresses.

9. The controller of claim 8 , wherein the access information includes a host memory map table.

10. The controller of claim 9 , wherein the processor generates the host memory map table by mapping the virtual addresses to the host memory physical addresses corresponding to the plurality of sub memory regions.

11. The controller of claim 8 , wherein the set size is a data size unit to be processed in the nonvolatile memory device.

12. The controller of claim 10 , wherein the processor generates the host memory map table by setting indexes to the host memory physical addresses and mapping the virtual addresses to the set indexes.

13. The controller of claim 12 , wherein the indexes are offset values from the lowest host memory physical address among the host memory physical addresses.

14. The controller of claim 10 , wherein the write command includes information of a size of the write data and the host memory physical addresses corresponding to the plurality of sub memory regions, and wherein the host memory map table is generated based on the information.

15. A controller which controls a nonvolatile memory device, the controller comprising: a first interface configured to receive, from a host, a write command for storing write data, which is currently stored in at least one memory region among a plurality of memory regions in a host memory; a first processor configured to generate a host memory map table by mapping virtual addresses to host memory physical addresses corresponding to the at least one memory region; a second interface configured to transmit the write data, stored in the at least one memory region, to the nonvolatile memory device; and a second processor configured to control the second interface to access the at least one memory region based on the host memory map table, wherein the controller identifies the at least one memory region in the host memory with reference to the host memory physical addresses.

16. The controller of claim 15 , wherein the first processor generates the host memory map table by mapping the virtual addresses to the host memory physical addresses corresponding to a plurality of sub memory regions within the at least one memory region, each of the plurality of sub memory regions having a set size.

17. The controller of claim 16 , wherein the set size is a data size unit to be processed in the nonvolatile memory device.

18. The controller of claim 16 , wherein the first processor generates the host memory map table by setting indexes to the host memory physical addresses and mapping the virtual addresses to the set indexes.

19. The controller of claim 18 , wherein the indexes are offset values from the lowest host memory physical address among the host memory physical addresses.

20. The controller of claim 15 , wherein the write command includes information of a size of the write data and the host memory physical addresses corresponding to a plurality of sub memory regions within the at least one memory region, each of the sub memory regions having a set size, and wherein the first processor generates, based on the information, the host memory map table by mapping the virtual addresses to the host memory physical addresses corresponding to the plurality of sub memory regions.