Preventing Read Disturbance Accumulation in a Cache Memory

1. A method for preventing read disturbance accumulation in a cache memory, the method comprising: accessing a plurality of data lines in a cache set, each of the plurality of data lines comprising a respective data field of a plurality of data fields and a respective error correction code (ECC) field of a plurality of ECC fields; generating a plurality of corrected data from a plurality of initial data stored in the plurality of data fields based on a plurality of ECCs stored in the plurality of ECC fields utilizing an ECC decoding unit; and selecting a requested corrected data of the plurality of corrected data based on a requested way of a plurality of ways, each of the plurality of ways associated with a respective data line of the plurality of data lines, wherein selecting the requested corrected data comprises: obtaining the requested way by comparing each of a plurality of tags associated with the plurality of ways with an input tag of the plurality of tags, the input tag associated with the requested way; and multiplexing the requested corrected data to an output of a data multiplexer by: loading each of the plurality of corrected data to a respective input of the data multiplexer; and loading the requested way to a selector input of the data multiplexer, the requested way associated with the requested corrected data.

2. The method of claim 1 , wherein generating the plurality of corrected data comprises generating each of the plurality of corrected data from a respective initial data of the plurality of initial data based on a respective ECC of the plurality of ECCs, the respective initial data stored in a respective data field of the plurality of data fields and the respective ECC stored in a respective ECC field of the plurality of ECC fields.

3. The method of claim 2 , wherein generating each of the plurality of corrected data comprises correcting each of the plurality of initial data by connecting each respective ECC decoder of a plurality of ECC decoders to a respective data line of the plurality of data lines.

4. The method of claim 2 , wherein generating each of the plurality of corrected data comprises sequentially correcting each of the plurality of initial data by sequentially coupling each of the plurality of data lines to an ECC decoder via an ECC multiplexer by sequentially routing each of the plurality of initial data to an input of the ECC decoder utilizing a selector input of the ECC multiplexer.

5. The method of 1 , wherein obtaining the requested way comprises: generating a plurality of comparator outputs by loading each of the plurality of tags to a respective input of a comparator unit; and generating a selector output associated with the requested way by loading the plurality of comparator outputs to an input of a selector unit.

6. The method of claim 5 , wherein generating the plurality of comparator outputs comprises generating each of the plurality of comparator outputs by: loading each respective tag of the plurality of tags to a respective first input of a respective comparator circuit of a plurality of comparator circuits; and loading the input tag to a second input of each of the plurality of comparator circuits.

7. The method of claim 5 , wherein generating the plurality of comparator outputs comprises generating each of the plurality of comparator outputs by: sequentially loading each of the plurality of tags to a first input of a comparator circuit via a tag multiplexer utilizing a selector input of the tag multiplexer; and loading the input tag to a second input of the comparator circuit.

8. The method of claim 5 , wherein generating the selector output comprises generating an encoded data associated with the requested way by encoding the plurality of comparator outputs utilizing an encoder.

9. The method of claim 1 , wherein accessing the plurality of data lines comprises accessing each of the plurality of data lines by accessing a storage element of a spin-transfer torque magnetic random-access memory (STT-MRAM) cell via an access element of the STT-MRAM cell coupled to the storage element.

10. A cache memory, comprising: a cache set comprising a plurality of data lines, each of the plurality of data lines comprising a respective data field of a plurality of data fields and a respective ECC field of a plurality of ECC fields; an error correction code (ECC) decoding unit comprising a plurality of ECC decoders, an input of each respective ECC decoder of the plurality of ECC decoders connected to a respective data line of the plurality of data lines, each respective ECC decoder configured to generate a respective corrected data of a plurality of corrected data from a respective initial data of a plurality of initial data based on a respective ECC of the plurality of ECCs, the respective initial data stored in a respective data field of the plurality of data fields and the respective ECC stored in a respective ECC field of the plurality of ECC fields; a data multiplexer configured to select a requested corrected data of the plurality of corrected data based on a requested way of a plurality of ways, each of the plurality of ways associated with a respective data line of the plurality of data lines; a comparator unit configured to generate a plurality of comparator outputs by comparing each of a plurality of tags associated with the plurality of ways with an input tag of the plurality of tags, the input tag associated with the requested way, the comparator unit comprising a plurality of comparator circuits, each of the plurality of comparator circuits comprising: a first input comprising a respective tag of the plurality of tags; and a second input comprising the input tag; and a selector unit comprising an encoder configured to generate an encoded data associated with the requested way by encoding the plurality of comparator outputs.

11. The cache memory of claim 10 , wherein each of the plurality of data lines comprises a spin-transfer torque magnetic random-access memory (STT-MRAM) cell, the STT-MRAM cell comprising: an access element coupled to a respective ECC decoder of the plurality of ECC decoders; and a storage element coupled to the access element.

12. A circuit for preventing read disturbance accumulation in a cache memory, the circuit comprising: an error correction code (ECC) decoding unit configured to: access a plurality of data lines in a cache set, each of the plurality of data lines comprising a respective data field of a plurality of data fields and a respective ECC field of a plurality of ECC fields; and generate a plurality of corrected data from a plurality of initial data stored in the plurality of data fields based on a plurality of ECCs stored in the plurality of ECC fields; a data multiplexer configured to select a requested corrected data of the plurality of corrected data based on a requested way of a plurality of ways, each of the plurality of ways associated with a respective data line of the plurality of data lines a comparator unit configured to generate a plurality of comparator outputs by comparing each of a plurality of tags associated with the plurality of ways with an input tag of the plurality of tags, the input tag associated with the requested way; and a selector unit configured to generate a selector output associated with the requested way.

13. The circuit of claim 12 , wherein the ECC decoding unit comprises a plurality of ECC decoders, each respective ECC decoder of the plurality of ECC decoders connected to a respective data line of the plurality of data lines, each respective ECC decoder configured to generate a respective corrected data of the plurality of corrected data from a respective initial data of the plurality of initial data based on a respective ECC of the plurality of ECCs, the respective initial data stored in a respective data field of the plurality of data fields and the respective ECC stored in a respective ECC field of the plurality of ECC fields.

14. The circuit of claim 12 , wherein the ECC decoding unit comprises: an ECC multiplexer; an ECC decoder configured to sequentially generate each of the plurality of corrected data from each respective initial data of the plurality of initial data based on each respective ECC of the plurality of ECCs by being sequentially connected to each respective data line of the plurality of data lines via the ECC multiplexer utilizing a selector input of the ECC multiplexer, each respective initial data stored in a respective data field of the plurality of data fields and each respective ECC stored in a respective ECC field of the plurality of ECC fields; and an ECC demultiplexer configured to sequentially route each respective corrected data of the plurality of corrected data from an output of the ECC decoder to a respective output of the ECC demultiplexer utilizing a selector input of the ECC demultiplexer.

15. The circuit of claim 12 , wherein the comparator unit comprises a plurality of comparator circuits, each of the plurality of comparator circuits comprising: a first input comprising a respective tag of the plurality of tags; and a second input comprising the input tag.

16. The circuit of claim 12 , wherein the comparator unit comprises: a comparator circuit comprising a first input and a second input comprising the input tag; a tag multiplexer configured to sequentially load each of the plurality of tags to the first input utilizing a selector input of the tag multiplexer; and a tag demultiplexer configured to sequentially route an output of the comparator circuit to each respective output of the tag demultiplexer utilizing a selector input of the tag demultiplexer, each respective output of the tag demultiplexer associated with a respective tag of the plurality of tags.

17. The circuit of claim 12 , wherein the selector unit comprises an encoder configured to generate an encoded data associated with the requested way by encoding the plurality of comparator outputs.

18. The circuit of claim 12 , wherein the ECC decoding unit is further configured to access each of the plurality of data lines by accessing a storage element of a spin-transfer torque magnetic random-access memory (STT-MRAM) cell via an access element of the STT-MRAM cell coupled to the storage element.