Connection Interface Circuit, Memory Storage Device and Phase-Locked Loop Circuit Calibration Method

1. A connection interface circuit for connecting a memory storage device to a host system, the connection interface circuit comprising: a calibration circuit, configured to provide a jitter signal; a jitter generation circuit, configured to receive a first signal from the host system and generate a second signal according to the first signal and the jitter signal; and a phase-locked loop circuit, coupled to the jitter generation circuit and the calibration circuit and configured to perform a phase-lock operation on the second signal to generate a third signal, wherein the calibration circuit is further configured to calibrate an electrical parameter of the phase-locked loop circuit according to a variation of a time difference between the first signal and the third signal, wherein the time difference comprises a first time difference and a second time difference, the first time difference is different from the second time difference, and the calibration circuit comprises: a jitter control circuit, configured to provide the jitter signal; a time to digit converter circuit, configured to detect the first time difference and the second time difference and generate a digital value according to the first time difference and the second time difference; and a control circuit, coupled to the jitter control circuit and the time to digit converter circuit and calibrating the electrical parameter of the phase-locked loop circuit according to the digital value.

2. The connection interface circuit according to claim 1 , wherein a frequency of the jitter signal is not higher than a frequency of the first signal.

3. The connection interface circuit according to claim 1 , wherein the operation that the calibration circuit calibrates the electrical parameter of the phase-locked loop circuit according to the variation of the time difference between the first signal and the third signal comprises: adjusting at least one circuit parameter of the phase-locked loop circuit to calibrate a loop bandwidth or a loop jitter peaking of the phase-locked loop circuit.

4. The connection interface circuit according to claim 3 , wherein the operation that the calibration circuit adjusts the at least one circuit parameter of the phase-locked loop circuit comprises: adjusting at least one of a current, an impedance and a gain on a close loop path of the phase-locked loop circuit.

5. The connection interface circuit according to claim 1 , wherein the digital value reflects a range of time offset caused by the jitter signal on the second signal.

6. The connection interface circuit according to claim 1 , wherein the operation that the calibration circuit calibrates the electrical parameter of the phase-locked loop circuit according to the variation of the time difference between the first signal and the third signal comprises: setting a frequency of the jitter signal to a first frequency; after performing the phase-lock operation on the second signal generated according to the first signal and the jitter signal having the first frequency, comparing the first signal and the third signal to generate a first digital value; determining a target value according to the first digital value; setting the frequency of the jitter signal to a second frequency, wherein the second frequency is different from the first frequency; after performing the phase-lock operation on the second signal generated according to the first signal and the jitter signal having the second frequency, comparing the first signal and the third signal to generate a second digital value; and calibrating the electrical parameter of the phase-locked loop circuit according to the target value and the second target value.

7. The connection interface circuit according to claim 1 , wherein the first signal is an initial signal for establishing a connection between the host system and the memory storage device in a handshake stage.

8. The connection interface circuit according to claim 1 , wherein the first signal is a test signal for calibrating the phase-locked loop circuit in a test stage.

9. The connection interface circuit according to claim 1 , wherein the jitter signal is configured to adjust the first signal so that at least one rising edge or at least one falling edge of a bitstream of the second signal has a different amount of time offset.

10. A memory storage device, comprising: a connection interface unit, configured to couple to a host system; a rewritable non-volatile memory module; and a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the connection interface unit comprises a phase-locked loop circuit, wherein the connection interface unit is configured to receive a first signal from the host system, wherein the connection interface unit is further configured to generate a jitter signal, wherein the connection interface unit is further configured to generate a second signal according to the first signal and the jitter signal, wherein the phase-locked loop circuit is configured to perform a phase-lock operation on the second signal to generate a third signal, wherein the connection interface unit is further configured to calibrate an electrical parameter of the phase-locked loop circuit according to a variation of a time difference between the first signal and the third signal, wherein the operation that the connection interface unit calibrates the electrical parameter of the phase-locked loop circuit according to the variation of the time difference between the first signal and the third signal comprises: detecting a first time difference between the first signal and the third signal; detecting a second time difference between the first signal and the third signal, wherein the first time difference is different from the second time difference; generating a digital value according to the first time difference and the second time difference; and calibrating the electrical parameter of the phase-locked loop circuit according to the digital value.

11. The memory storage device according to claim 10 , wherein a frequency of the jitter signal is not higher than a frequency of the first signal.

12. The memory storage device according to claim 10 , wherein the operation that the connection interface unit calibrates the electrical parameter of the phase-locked loop circuit according to the variation of the time difference between the first signal and the third signal comprises: adjusting at least one circuit parameter of the phase-locked loop circuit to calibrate a loop bandwidth or a loop jitter peaking of the phase-locked loop circuit.

13. The memory storage device according to claim 12 , wherein the operation that the connection interface unit adjusts the at least one circuit parameter of the phase-locked loop circuit comprises: adjusting at least one of a current, an impedance and a gain on a close loop path of the phase-locked loop circuit.

14. The memory storage device according to claim 10 , wherein the digital value reflects a time offset range caused by the jitter signal on the second signal.

15. The memory storage device according to claim 10 , wherein the operation that the connection interface unit calibrates the electrical parameter of the phase-locked loop circuit according to the variation of the time difference between the first signal and the third signal comprises: setting a frequency of the jitter signal to a first frequency; after performing the phase-lock operation on the second signal generated according to the first signal and the jitter signal having the first frequency, comparing the first signal and the third signal to generate a first digital value; determining a target value according to the first digital value; setting the frequency of the jitter signal to a second frequency, wherein the second frequency is different from the first frequency; after performing the phase-lock operation on the second signal generated according to the first signal and the jitter signal having the second frequency, comparing the first signal and the third signal to generate a second digital value; and calibrating the electrical parameter of the phase-locked loop circuit according to the target value and the second target value.

16. The memory storage device according to claim 10 , wherein the first signal is an initial signal for establishing a connection between the host system and the memory storage device in a handshake stage.

17. The memory storage device according to claim 10 , wherein the first signal is a test signal for calibrating the phase-locked loop circuit in a test stage.

18. The memory storage device according to claim 10 , wherein the jitter signal is configured to adjust the first signal so that at least one rising edge or at least one falling edge of a bitstream of the second signal has a different amount of time offset.

19. A phase-locked loop circuit calibration method for a memory storage device comprising a rewritable non-volatile memory module, the phase-locked loop circuit calibration method comprising: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and calibrating an electrical parameter of the phase-locked loop circuit according to a variation of a time difference between the first signal and the third signal, wherein the step of calibrating the electrical parameter of the phase-locked loop circuit according to the variation of the time difference between the first signal and the third signal comprises: detecting a first time difference between the first signal and the third signal; detecting a second time difference between the first signal and the third signal, wherein the first time difference is different from the second time difference; generating a digital value according to the first time difference and the second time difference; and calibrating the electrical parameter of the phase-locked loop circuit according to the digital value.

20. The phase-locked loop circuit calibration method according to claim 19 , wherein a frequency of the jitter signal is not higher than a frequency of the first signal.

21. The phase-locked loop circuit calibration method according to claim 19 , wherein the step of calibrating the electrical parameter of the phase-locked loop circuit according to the variation of the time difference between the first signal and the third signal comprises: adjusting at least one circuit parameter of the phase-locked loop circuit to calibrate a loop bandwidth or a loop jitter peaking of the phase-locked loop circuit.

22. The phase-locked loop circuit calibration method according to claim 21 , wherein the step of adjusting the at least one circuit parameter of the phase-locked loop circuit comprises: adjusting at least one of a current, an impedance and a gain on a close loop path of the phase-locked loop circuit.

23. The phase-locked loop circuit calibration method according to claim 19 , wherein the digital value reflects a time offset range caused by the jitter signal on the second signal.

24. The phase-locked loop circuit calibration method according to claim 19 , wherein the step of calibrating the electrical parameter of the phase-locked loop circuit according to the variation of the time difference between the first signal and the third signal comprises: setting a frequency of the jitter signal to a first frequency; after performing the phase-lock operation on the second signal generated according to the first signal and the jitter signal having the first frequency, comparing the first signal and the third signal to generate a first digital value; determining a target value according to the first digital value; setting the frequency of the jitter signal to a second frequency, wherein the second frequency is different from the first frequency; after performing the phase-lock operation on the second signal generated according to the first signal and the jitter signal having the second frequency, comparing the first signal and the third signal to generate a second digital value; and calibrating the electrical parameter of the phase-locked loop circuit according to the target value and the second target value.

25. The phase-locked loop circuit calibration method according to claim 19 , wherein the first signal is an initial signal for establishing a connection between the host system and the memory storage device in a handshake stage.

26. The phase-locked loop circuit calibration method according to claim 19 , wherein the first signal is a test signal for calibrating the phase-locked loop circuit in a test stage.

27. The phase-locked loop circuit calibration method according to claim 19 , wherein the jitter signal is configured to adjust the first signal so that at least one rising edge or at least one falling edge of a bitstream of the second signal has a different amount of time offset.