Cybersecurity Penetration Test Platform

1. A method of testing a plurality of circuits to determine open surfaces, the method comprising: receiving one or more of attack techniques, and known open surfaces; carrying out attacks on a circuit to determine vulnerable surfaces of the circuit; determining when new open surfaces exist in the circuit; updating an attack plan based on the new open surfaces; carrying out the attack plan; generating a report of the open and vulnerable surfaces; and updating a regression test suite to include new attack techniques against newly discovered open surfaces of the circuit.

2. The method of claim 1 , further comprising, after carrying out the attacks: determining that when no new open surfaces exist in the circuit, not updating the attack plan; and carrying out of the attack plan.

3. The method of claim 2 , further comprising, after carrying out the attack plan: generating a report of the determined open surfaces for the circuit.

4. The method of claim 1 , wherein the report comprises newly discovered attack surfaces, or newly determined open surfaces, or both.

5. The method of claim 4 , further comprising storing the newly discovered attack surfaces, or the newly discovered open surfaces in the regression test suite.

6. The method of claim 1 , further comprising determining when a service on an open port is known; and after the determining when the service on the open surface is known, executing an exploitation service on the open port.

7. A system for testing a plurality of components to determine vulnerability and open surfaces, the system comprising: a test automation platform, comprising: a memory that stores executable instructions; and a processor configured to execute the instructions retrieved from the memory, wherein when executed by the processor, the instructions cause the processor to: receive one or more of attack techniques, known open surfaces; carry out attacks on a circuit to determine vulnerable surfaces of the circuit; determine when new open surfaces exist in the circuit; update an attack plan based on the new open surfaces; carry out the attack plan; generate a report of the open and vulnerable surfaces; and update a repository to include new attack techniques against discovered new open surfaces for the circuit.

8. The system of claim 7 , wherein the memory that stores executable instructions further comprises instructions, when executed, further cause the processor to: determine when no new open surfaces exist in the circuit, and not update the attack plan; and perform the carry out of the attack plan.

9. The system of claim 7 , wherein the memory that stores executable instructions further comprises instructions, when executed, further cause the processor to: generate a report of the determined open surfaces for the circuit after the performing of the carry out of the attack plan.

10. The system of claim 7 , wherein the memory further comprises: a security tool kit; a test suite; and an attack database.

11. The system of claim 10 , wherein the test suite and the attack database comprise at least a portion of the instructions.

12. The system of claim 10 , wherein the security tool kit comprises the instructions that carry out the attack plan.

13. The system of claim 10 , further comprising an emulator, comprising: a plurality of communication layers, each of the communication layers adapted to transmit the attack plan to the circuit based on a protocol specific to the circuits.

14. The system of claim 13 , wherein the processor is a first processor, the circuit is a first circuit, and the system further comprises an enterprise platform, comprising: a second processor configured to execute the instructions retrieved from the memory, wherein the instructions, when executed, cause the first processor to carry out testing of a second circuit.

15. The system of claim 10 , wherein the memory comprises a security test suite and an attack database.

16. The system of claim 10 , wherein the memory further comprises a customer threat library and a customer threat database.

17. The system of claim 10 , wherein the repository is a regression test suite.

18. A non-transitory computer-readable storage medium that stores machine executable instructions executable on a processor, which when executed by the processor cause the processor to perform a method, the method comprising: receiving one or more of attack techniques, and known open surfaces; carrying out attacks on a circuit to determine vulnerable surfaces of the circuit; determining when new open surfaces exist in the circuit; updating an attack plan based on the new open surfaces; carrying out the attack plan; generating a report of the open and vulnerable surfaces; and updating a regression test suite to include new attack techniques against newly discovered open surfaces of the circuit.

19. The non-transitory computer-readable medium of claim 18 , wherein the method further comprises, after carrying out the attacks: determining that when no new open surfaces exist in the circuit, not updating the attack plan; and carrying out of the attack plan.

20. The non-transitory computer-readable medium of claim 18 , wherein the method further comprises, after carrying out the attacks: generating a report of the determined open surfaces for the circuit.