Scan Synchronous-Write-Through Testing Architectures for a Memory Device

1. A method for operating a memory storage device, the memory storage device including a memory array, circuitry under test, and circuitry not under test, the method comprising: disabling, by the memory storage device, the memory array and the circuitry not under test; selecting, by first multiplexing circuitry within the memory storage device, a serial sequence of data or a parallel sequence of data to be an input sequence of data; providing, by first latching circuitry within the memory storage device, the input sequence of data in accordance with a memory clocking signal; operating on, by the circuitry under test, the input sequence of data to provide a serial sequence of output data or a parallel sequence of output data; providing, by second latching circuitry within the memory storage device, the input sequence of data as a second serial sequence of output data in accordance with the memory clocking signal; and selecting, by second multiplexing circuitry within the memory storage device, the serial sequence of output data, the parallel sequence of output data, or the second serial sequence of output data as an output sequence of data.

2. The method of claim 1 , wherein the selecting the serial sequence of output data, the parallel sequence of output data, or the second serial sequence of output data as the output sequence of data comprises: selecting, by the second multiplexing circuitry, the parallel sequence of output data or the second serial sequence of output data as the output sequence of data, and wherein the method further comprises: providing, by the second multiplexing circuitry, the output sequence of data to functional logic circuitry coupled to the memory storage device to electronically stress the functional logic circuitry to test for a presence of a manufacturing fault in the functional logic circuitry.

3. The method of claim 1 , wherein the selecting the serial sequence of output data, the parallel sequence of output data, or the second serial sequence of output data as the output sequence of data comprises: selecting, by the second multiplexing circuitry, the serial sequence of output data as the output sequence of data, and wherein the method further comprises: providing, by the second multiplexing circuitry, the output sequence of data to functional logic circuitry coupled to the memory storage device to analyze the output sequence of data to determine whether the circuitry under test operates as expected.

4. The method of claim 3 , wherein the circuitry under test operates as expected when the output sequence of data matches an expected value of the output sequence of data and operates unexpectedly when the output sequence of data does not match the expected value of the output sequence of data.

5. The method of claim 1 , wherein the circuitry not under test comprises one or more of: row selection circuitry, column selection circuitry, and a sense amplifier/write driver, and wherein the disabling comprises: disabling, by the memory storage device, the row selection circuitry, the column selection circuitry, or the sense amplifier/write driver.

6. The method of claim 1 , wherein the circuitry under test comprises one or more of: an output latch, a sense amplifier/write driver, and third multiplexing circuitry, and wherein the operating on the input sequence of data comprises: operating on, by the output latch, the sense amplifier/write driver, or the third multiplexing circuitry, the input sequence of data to provide the serial sequence of output data or the parallel sequence of output data.

7. The method of claim 1 , wherein the providing the input sequence of data in accordance with the memory clocking signal comprises: providing, by the first latching circuitry, the input sequence of data upon a rising edge of the memory clocking signal, and wherein the providing the input sequence of data as the second serial sequence of output data in accordance with the memory clocking signal comprises: providing, by the second latching circuitry, the input sequence of data as the second serial sequence of output data upon a falling edge of the memory clocking signal.

8. The method of claim 1 , wherein the providing the input sequence of data as the second serial sequence of output data comprises: passing through the input sequence of data to provide the second serial sequence of output data in accordance with the memory clocking signal.

9. A memory storage device, comprising: first latching circuitry configured to: provide a serial sequence of input data in a shift mode of operation or a scan mode of operation, and provide a parallel sequence of input data in a capture mode of operation; a memory device configured to: operate on the serial sequence of input data to provide a serial sequence of output data in the shift mode of operation, and operate on the parallel sequence of input data to provide a parallel sequence of output data in the capture mode of operation; second latching circuitry configured to pass through the serial sequence of input data to provide a second serial sequence of output data in the scan mode of operation; and multiplexing circuitry configured to: provide the serial sequence of output data in the shift mode of operation, provide the parallel sequence of output data in the capture mode of operation, and provide the second serial sequence of output data in the scan mode of operation.

10. The memory storage device of claim 9 , wherein the multiplexing circuitry is configured to: provide the parallel sequence of output data in the capture mode of operation or the second serial sequence of output data in the scan mode of operation to electronically stress functional logic circuitry coupled to the memory storage device to test for a presence of a manufacturing fault in the functional logic circuitry.

11. The memory storage device of claim 9 , wherein the multiplexing circuitry is configured to provide the serial sequence of output data in the shift mode of operation to functional logic circuitry coupled to the memory storage device to analyze the output sequence of data to determine whether the circuitry under test operates as expected.

12. The memory storage device of claim 11 , wherein the circuitry under test operates as expected when the output sequence of data matches an expected value of the output sequence of data and operates unexpectedly when the output sequence of data does not match the expected value of the output sequence of data.

13. The memory storage device of claim 9 , wherein the memory device comprises one or more of: row selection circuitry, column selection circuitry, and a sense amplifier/write driver, and wherein the row selection circuitry, the column selection circuitry, or the sense amplifier/write driver are configured to be disabled in the shift mode of operation and the capture mode of operation.

14. The memory storage device of claim 9 , wherein the circuitry under test comprises one or more of: an output latch, a sense amplifier/write driver, and third multiplexing circuitry and wherein the output latch, the sense amplifier/write driver, or the third multiplexing circuitry is configured to: operate on the serial sequence of input data to provide the serial sequence of output data in the shift mode of operation, and operate on the parallel sequence of input data to provide the parallel sequence of output data in the capture mode of operation.

15. The memory storage device of claim 9 , wherein the first latching circuitry is configured to: provide the serial sequence of input data upon a rising edge of a memory clocking signal, and provide a parallel sequence of input data upon the rising edge of a memory clocking signal, and wherein the second latching circuitry is configured to pass through the serial sequence of input data upon a falling edge of the memory clocking signal.

16. A system, comprising: first functional logic circuitry configured to provide a serial input sequence of data or a parallel input sequence of data; a memory storage device configured to: operate on the serial input sequence of data to provide a first serial output sequence of data in a first mode of operation; operate on the parallel input sequence of data to provide a parallel output sequence of data in a second mode of operation; and pass-through the serial input sequence of data to provide a second serial output sequence of data in a third mode of operation; and second functional logic circuitry configured to: analyze the first serial output sequence of data to determine whether the memory storage device operates as expected or unexpectedly; and be electronically stressed by the parallel output sequence of data or the second serial output sequence of data to test for a presence of a manufacturing fault in the second functional logic circuitry.

17. The system of claim 16 , wherein the memory storage device operates as expected when the output sequence of data matches an expected value of the output sequence of data and operates unexpectedly when the output sequence of data does not match the expected value of the output sequence of data.

18. The system of claim 16 , wherein the memory storage device comprises one or more of: row selection circuitry, column selection circuitry, and a sense amplifier/write driver, and wherein the row selection circuitry, the column selection circuitry, or the sense amplifier/write driver are configured to be disabled in the first mode of operation and the second mode of operation.

19. The system of claim 16 , wherein the circuitry under test comprises one or more of: an output latch, a sense amplifier/write driver, and third multiplexing circuitry and wherein the output latch, the sense amplifier/write driver, or the third multiplexing circuitry is configured to: operate on the serial sequence of input data to provide the serial sequence of output data in the first mode of operation, and operate on the parallel sequence of input data to provide the parallel sequence of output data in the second mode of operation.

20. The system of claim 16 , wherein the first functional logic circuitry is configured to provide the serial input sequence of data in the first mode of operation or the third mode of operation or a parallel input sequence of data in the second mode of operation.