Static Identifications in Object-based Memory Access

1. A computer system, comprising: a register of a first predetermined width, the register to store an address having: a first portion identifying an object; and a second portion identifying an offset relative to the object; and an execution unit configured to execute an instruction using the address; wherein when the first portion has a first static identifier, a first predetermined property of a first class of objects pre-associated with the first static identifier is used in executing the instruction, wherein the first class of objects is first applications using a first address space having a second predetermined width that is smaller than the first predetermined width; wherein when the first portion has a second static identifier, a second predetermined property of a second class of objects pre-associated with the second static identifier is used in executing the instruction, wherein the second class of objects is second applications using a second address space having a third predetermined width that is smaller than the first predetermined width and different from the second predetermined width.

2. The computer system of claim 1 , wherein the first predetermined width is 128 bits; and the second predetermined width is one of: 64 bits and 32 bits.

3. The computer system of claim 2 , wherein when the first static identifier has a value of one, the second predetermined width is 64 bits.

4. The computer system of claim 2 , wherein when the first static identifier has a value of one, the second predetermined width is 32 bits.

5. The computer system of claim 1 , wherein the first predetermined property is used in address conversion during executing instructions of the object.

6. The computer system of claim 5 , wherein the address conversion includes converting an address from the second predetermined width to the first predetermined width.

7. The computer system of claim 6 , wherein converting the address from the second predetermined width to the first predetermined width is performed using the static identifier as an object identifier and the address of the second predetermined width as an offset.

8. The computer system of claim 1 , wherein the first class of objects is in a kernel of an operating system of the computer system.

9. The computer system of claim 8 , wherein when the first static identifier has a value of zero.

10. The computer system of claim 1 , wherein the instruction is loaded using the address for execution.

11. The computer system of claim 1 , wherein execution of the instruction operates on a data item obtained from a memory location identified by the address.

12. The computer system of claim 1 , wherein the first predetermined property is used to adjust a security operation during executing instructions of the object.

13. The computer system of claim 1 , wherein the first predetermined property is used to adjust a priority during executing instructions of the object.

14. A method, comprising: receiving, in a processor, a first address in a first address space having a first predetermined width; determining, by the processor, a first predefined identifier predefined to represent the first address space; combining, by the processor, the first predefined identifier and the first address to generate a second address having a second predetermined width larger than the first predetermined width, wherein the second address has a first object identifier portion and a first offset portion, and the first object identifier portion of the second address contains the first predefined identifier representing the first address space and the first offset portion of the second address corresponds to the first address; receiving in the processor, a third address in a second address space having a third predetermined width different from the first predetermined width; determining, by the processor, a second predefined identifier predefined to represent the second address space; and combining, by the processor, the second predefined identifier and the third address to generate a fourth address having a fourth predetermined width larger than the first predetermined width and larger than the third predetermined width, wherein the fourth address has a second object identifier portion and a second offset portion, the second object identifier portion of the fourth address contains the second predefined identifier representing the second address space and the second offset portion of the fourth address corresponds to the third address.

15. The method of claim 14 , wherein the second predetermined width is 128 bits; and the first predetermined width is one of: 64 bits and 32 bits.

16. The method of claim 15 , wherein the first object identifier portion of the second address has 64 bits; and the byte offset portion of the second address has 64 bits.

17. A computer system: a processor; and a memory address system comprising a plurality of memory addresses configured to cause the processor to perform operations based on data provided in a respective one of the plurality of memory addresses, wherein: each of the plurality of memory addresses are of a first predetermined width, a first memory address of the plurality of memory addresses in the memory address system includes a first object identifier portion and a first offset portion, wherein a first predetermined value provided in the first object identifier portion represents a first object property pre-associated with the first predetermined value; the first object property identifies a first subset of the plurality of memory addresses of a second predetermined width that is smaller than the first predetermined width; a second memory address of the plurality of memory addresses in the memory address system includes a second object identifier portion and a second offset portion, wherein a second predetermined value provided in the second object identifier portion represents a second object property pre-associated with the second predetermined value; and the second object property identifies a second subset of the plurality of memory addresses of a third predetermined width that is different from the second predetermined width and that is smaller than the first predetermined width.

18. The computer system of claim 17 , wherein the first object property identifies a kernel of an operating system.