Continuous Time Linear Equalization System and Method

1. A continuous time linear equalization training method, comprising: determining, using a decision feedback equalization (“DFE”) training block, a voltage value for one or more resistor values; determining, using the DFE training block, a voltage value for one or more capacitor values; identifying a voltage difference between the voltage value for one or more resistor values and the voltage value for one or more capacitor values; and iteratively performing the determining of the voltage value and identifying of the voltage difference for each of the plurality of capacitor values until the voltage difference is at one or more minimum values to generate one or more optimal resistor and capacitor coefficients for a continuous time linear equalization filter.

2. The continuous time linear equalization training method of claim 1 , further comprising: storing the optimal resistor and capacitor coefficient in a register.

3. The continuous time linear equalization training method of claim 1 , further comprising: providing the optimal resistor and capacitor coefficient to a front end receiver.

4. The continuous time linear equalization training method of claim 1 , wherein the optimal resistor and capacitor coefficient are generated without calculating an eye height and width for all resistor and capacitor values.

5. The continuous time linear equalization training method of claim 3 , wherein the front end receiver includes a one tap unrolled DFE receiver.

6. The continuous time linear equalization training method of claim 1 , wherein the front end receiver includes an auto-zero calibration receiver, higher voltage reference receiver, and a lower voltage reference receiver.

7. The continuous time linear equalization training method of claim 6 , further comprising: performing an auto-zeroing operation using the calibration receiver.

8. A non-transitory computer readable storage medium having stored thereon instructions, which when executed result in one or more operations, the operations comprising: providing a front end receiver and a decision feedback equalization (“DFE”) training block; determining using the DFE training block, a voltage value for one or more resistor values; determining, using the DFE training block, a voltage value for one or more capacitor values; identifying a voltage difference between the voltage value for one or more resistor values and the voltage value for one or more capacitor values; iteratively performing the determining of the voltage value and identifying of the voltage difference for each of the plurality of capacitor values until the voltage difference is at one or more minimum values to generate one or more optimal resistor and capacitor coefficients for a continuous time linear equalization filter; and providing the optimal resistor and capacitor coefficient to a calibration receiver.

9. The non-transitory computer readable medium of claim 8 , the operations further comprising: storing the optimal resistor and capacitor coefficient in a register.

10. The non-transitory computer readable medium of claim 8 , the operations further comprising: providing the optimal resistor and capacitor coefficient to the front end receiver.

11. The non-transitory computer readable medium of claim 8 , wherein the optimal resistor and capacitor coefficient are generated without calculating an eye height and width for all resistor and capacitor values.

12. The non-transitory computer readable medium of claim 8 , wherein the front end receiver includes a one tap unrolled receiver.

13. The non-transitory computer readable medium of claim 8 , wherein the front end receiver includes a calibration receiver, higher voltage reference receiver, and a lower voltage reference receiver.

14. The non-transitory computer readable medium of claim 13 , the operations further comprising: performing an auto-zeroing operation using the calibration receiver.

15. A system for continuous time linear equalization, comprising: a plurality of receivers; a multiplexer configured to receive one or more inputs from the plurality of receivers; DFE circuitry configured to receive one or more inputs from the multiplexer; one or more deserializers configured to receive one or more inputs from the multiplexer; and a multi-tap decision feedback equalization (“DFE”) training block configured to receive one or more inputs from the one or more deserializers and to determine a voltage value for one or more resistor values, the DFE training block further configured to determine a voltage value for one or more capacitor values and to identify a voltage difference, the DFE training block further configured to generate an optimal resistor and capacitor coefficient for a continuous time linear equalization filter based upon, at least in part, the voltage difference.

16. The continuous time linear equalization training system of claim 15 , further comprising: a register for storing the optimal resistor and capacitor coefficient.

17. The continuous time linear equalization training system of claim 15 , wherein the DFE training block is configured to provide the optimal resistor and capacitor coefficient to the front end receiver.

18. The continuous time linear equalization training system of claim 15 , wherein the optimal resistor and capacitor coefficient are generated without calculating an eye height and width for all resistor and capacitor values.

19. The continuous time linear equalization training system of claim 15 , wherein the front end receiver includes a one tap unrolled receiver.

20. The continuous time linear equalization training system of claim 15 , wherein the front end receiver includes a calibration receiver, higher voltage reference receiver, and a lower voltage reference receiver.