IC including Logic Tile, having Reconfigurable MAC Pipeline, and Reconfigurable Memory

1. An integrated circuit comprising: multiplier-accumulator circuitry, configurable in a concatenation architecture, to perform a plurality of multiply and accumulate operations, wherein the multiplier-accumulator circuitry includes a plurality of multiplier-accumulator circuits, wherein each multiplier-accumulator circuit includes: a multiplier to multiply data by a weight data and generate a product data, and an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add input data and the product data of the associated multiplier to generate sum data, and wherein the plurality of multiplier-accumulator circuits are connected in series to perform a plurality of concatenated multiply and accumulate operations; a switch interconnect network, coupled to the multiplier-accumulator circuitry, including a plurality of configurable multiplexers arranged in a plurality of switch matrices; first memory, coupled to the switch interconnect network and the multiplier-accumulator circuitry; second memory, coupled to the switch interconnect network and the multiplier-accumulator circuitry; weight memory to store weight data and to output the weight data to the multipliers; wherein, during a first data processing operation, a first plurality of the multiplier-accumulator circuits are serially connected into a first MAC pipeline to perform a plurality of concatenated multiply and accumulate operations of the first data processing operation, and wherein: during the first data processing operation (i) the first memory is coupled, via the switch interconnect network, to the first MAC pipeline to output data to the first MAC pipeline, and (ii) the second memory is coupled, via the switch interconnect network, to input data from the first MAC pipeline, and wherein, during the first data processing operation, the first memory is dedicated to write data to the first MAC pipeline and the second memory is dedicated to read data from the first MAC pipeline; and wherein, during a second data processing operation, a second plurality of the multiplier-accumulator circuits are serially connected into a second MAC pipeline to perform a plurality of concatenated multiply and accumulate operations of the second data processing operation, and wherein: during the second data processing operation (i) the first memory is coupled, via the switch interconnect network, to the second MAC pipeline to input data from the second MAC pipeline, and (ii) the second memory is coupled, via the switch interconnect network, to the second MAC pipeline to output data to the second MAC pipeline, and wherein, during the second data processing operation, the first memory is dedicated to read data from the second MAC pipeline and the second memory is dedicated to write data to the second MAC pipeline.

2. The integrated circuit of claim 1 wherein: after the first plurality of multiplier-accumulator circuits of the first MAC pipeline complete the first data processing operation, the second plurality of the multiplier-accumulator circuits are serially connected into the second MAC pipeline, in situ.

3. The integrated circuit of claim 1 wherein: the plurality of switch matrices of the switch interconnect network are arranged in a plurality of switch matrix stages interconnected in a hierarchical interconnect network.

4. The integrated circuit of claim 1 further including: configurable interface circuitry coupled to the switch interconnect network and the multiplier-accumulator circuitry, wherein the configurable interface circuitry includes one or more multiplexers, responsively configured, to connect the multiplier-accumulator circuits of the first MAC pipeline to the switch interconnect network during the first data processing operation.

5. The integrated circuit of claim 4 wherein: the multiplexers of the configurable interface circuitry are responsively configured, in situ, to connect the multiplier-accumulator circuits of the second MAC pipeline to the switch interconnect network during the second data processing operation.

6. The integrated circuit of claim 1 wherein: the configurable multiplexers of the switch interconnect network are responsively configured, in situ, to connect the multiplier-accumulator circuits of the second MAC pipeline to the configurable interface circuitry during the second data processing operation.

7. The integrated circuit of claim 1 wherein the plurality of multiplier-accumulator circuits are organized into a plurality of rows, wherein each row includes a plurality of serially interconnected multiplier-accumulator circuits, and the integrated circuit further includes: configurable interface circuitry coupled to the switch interconnect network and the multiplier-accumulator circuitry, wherein the configurable interface circuitry includes one or more multiplexers, responsively configured, to serially connect a predetermined number of rows of the multiplier-accumulator circuits into the first MAC pipeline during the first data processing operation.

8. The integrated circuit of claim 7 wherein: the multiplexers of the configurable interface circuitry are responsively configured to connect a predetermined number of rows of the multiplier-accumulator circuits into the second MAC pipeline during the second data processing operation.

9. The integrated circuit of claim 8 wherein: at least one row of the plurality of rows of multiplier-accumulator circuits of the first MAC pipeline is different from the plurality of rows of the multiplier-accumulator circuits of the second MAC pipeline, or at least one row of the plurality of rows of multiplier-accumulator circuits of the second MAC pipeline is different from the plurality of rows of the multiplier-accumulator circuits of the first MAC pipeline.

10. The integrated circuit of claim 1 wherein: immediately after the first plurality of multiplier-accumulator circuits of the first MAC pipeline complete the first data processing operation, the second plurality of the multiplier-accumulator circuits are serially connected into the second MAC pipeline, in situ.

11. An integrated circuit comprising: multiplier-accumulator circuitry, configurable in a concatenation architecture, to perform a plurality of multiply and accumulate operations, wherein the multiplier-accumulator circuitry includes a plurality of multiplier-accumulator circuits, wherein each multiplier-accumulator circuit includes: a multiplier to multiply data by a weight data and generate a product data, and an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add input data and the product data of the associated multiplier to generate sum data, and wherein the plurality of multiplier-accumulator circuits are connected in series to perform a plurality of concatenated multiply and accumulate operations; configurable interface circuitry, coupled to the plurality of multiplier-accumulator circuits of the multiplier-accumulator circuitry, to: responsively configure a first plurality of multiplier-accumulator circuits of the multiplier-accumulator circuitry into a first MAC pipeline to perform a first data processing operation, and responsively configure, in situ, a second plurality of multiplier-accumulator circuits of the multiplier-accumulator circuitry into a second MAC pipeline to perform a second data processing operation; first memory coupled, via the configurable interface circuitry, to the multiplier-accumulator circuitry; second memory coupled, via the configurable interface circuitry, to the multiplier-accumulator circuitry; weight memory to store the weight data and output the weight data to the multipliers; wherein, during the first data processing operation, the first plurality of the multiplier-accumulator circuits are serially connected into the first MAC pipeline to perform a plurality of concatenated multiply and accumulate operations of the first data processing operation, and wherein: during the first data processing operation (i) the first memory is coupled, via the configurable interface circuitry, to the first MAC pipeline to output data thereto, and (ii) the second memory is coupled, via the configurable interface circuitry, to input data therefrom, and wherein, during the first data processing operation, the first memory is dedicated to write data to the first MAC pipeline and the second memory is dedicated to read data from the first MAC pipeline; and wherein, during the second data processing operation, the second plurality of the multiplier-accumulator circuits are serially connected into the second MAC pipeline to perform a plurality of concatenated multiply and accumulate operations of the second data processing operation, and wherein: during the second data processing operation (i) the first memory is coupled, via the configurable interface circuitry, to the second MAC pipeline to input data therefrom, and (ii) the second memory is coupled, via the configurable interface circuitry, to the second MAC pipeline to output data thereto, and wherein, during the second data processing operation, the first memory is dedicated to read data from the second MAC pipeline and the second memory is dedicated to write data to the second MAC pipeline.

12. The integrated circuit of claim 11 wherein: after the first plurality of multiplier-accumulator circuits of the first MAC pipeline complete the first data processing operation, the second plurality of the multiplier-accumulator circuits are serially connected into the second MAC pipeline, in situ.

13. The integrated circuit of claim 11 wherein: the plurality of multiplier-accumulator circuits are organized into a plurality of rows, wherein each row includes a plurality of serially interconnected multiplier-accumulator circuits, and the configurable interface circuitry includes one or more multiplexers, responsively configured, to serially connect a predetermined number of rows of the multiplier-accumulator circuits into the first MAC pipeline during the first data processing operation.

14. The integrated circuit of claim 13 wherein: the multiplexers of the configurable interface circuitry are responsively configured to serially connect a predetermined number of rows of the multiplier-accumulator circuits into the second MAC pipeline during the second data processing operation.

15. The integrated circuit of claim 14 wherein: at least one row of the plurality of rows of multiplier-accumulator circuits of the first MAC pipeline is different from the plurality of rows of the multiplier-accumulator circuits of the second MAC pipeline, or at least one row of the plurality of rows of multiplier-accumulator circuits of the second MAC pipeline is different from the plurality of rows of the multiplier-accumulator circuits of the first MAC pipeline.

16. The integrated circuit of claim 11 wherein: immediately after the first plurality of multiplier-accumulator circuits of the first MAC pipeline complete the first data processing operation, the configurable interface circuitry serially connect, in situ, the second plurality of the multiplier-accumulator circuits into the second MAC pipeline.

17. An integrated circuit comprising: first memory; second memory; and a plurality of logic tiles, arranged in a plurality of rows and/or a plurality of columns, wherein the first memory and second memory are located external to the plurality of logic tiles, and wherein the logic tiles include: multiplier-accumulator circuitry to perform a plurality of multiply and accumulate operations, wherein the multiplier-accumulator circuitry includes a plurality of multiplier-accumulator circuits, wherein each multiplier-accumulator circuit includes: a multiplier to multiply data by a weight data and generate a product data, and an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add input data and the product data of the associated multiplier to generate sum data, and wherein the multiplier-accumulator circuits are connected in series to perform a plurality of concatenated multiply and accumulate operations; configurable interface circuitry, coupled to the plurality of multiplier-accumulator circuits of the multiplier-accumulator circuitry, to: responsively configure a first plurality of multiplier-accumulator circuits of the multiplier-accumulator circuitry into a first plurality of MAC pipelines to perform first data processing operations, and responsively configure, in situ, a second plurality of multiplier-accumulator circuits of the multiplier-accumulator circuitry into a second plurality of MAC pipelines to perform second data processing operations; wherein, during the first data processing operations, the first plurality of the multiplier-accumulator circuits are serially connected into the first plurality of MAC pipelines to perform a plurality of concatenated multiply and accumulate operations of the first data processing operations, and wherein: during the first data processing operations (i) the first memory is coupled, via the configurable interface circuitry, to the first MAC plurality of pipelines to output data to first MAC plurality of pipelines, and (ii) the second memory is coupled, via the configurable interface circuitry, to input data from the first plurality of MAC pipelines, and wherein, during the first data processing operations, the first memory is dedicated to write data to the first plurality of MAC pipelines and the second memory is dedicated to read data from the first plurality of MAC pipelines; and wherein, during the second data processing operations, the second plurality of the multiplier-accumulator circuits are serially connected into the second plurality of MAC pipelines to perform a plurality of concatenated multiply and accumulate operations of the second data processing operations, and wherein: during the second data processing operations (i) the first memory is coupled, via the configurable interface circuitry, to the second plurality of MAC pipelines to input data from the second plurality of MAC pipelines, and (ii) the second memory is coupled, via the configurable interface circuitry, to the second MAC pipelines to output data to the second plurality of MAC pipelines, and wherein, during the second data processing operations, the first memory is dedicated to read data from the second plurality of MAC pipelines and the second memory is dedicated to write data to the second plurality of MAC pipelines.

18. The integrated circuit of claim 17 wherein: the plurality of multiplier-accumulator circuits of the multiplier-accumulator circuitry of each logic tile are organized into a plurality of rows, wherein each row includes a plurality of serially interconnected multiplier-accumulator circuits, and the configurable interface circuitry of each logic tile includes one or more multiplexers, responsively configured, to serially connect a predetermined number of rows of the multiplier-accumulator circuits into the first plurality of MAC pipelines during the first data processing operations.

19. The integrated circuit of claim 18 wherein: the multiplexers of the configurable interface circuitry of each logic tile are responsively configured to serially connect a predetermined number of rows of the multiplier-accumulator circuits into the second plurality of MAC pipelines during the second data processing operations.

20. The integrated circuit of claim 19 wherein: at least one row of the plurality of rows of multiplier-accumulator circuits of the first plurality of MAC pipelines is different from the plurality of rows of the multiplier-accumulator circuits of the second plurality of MAC pipeline, or at least one the row of the plurality of rows of multiplier-accumulator circuits of the second plurality of MAC pipelines is different from the plurality of rows of the multiplier-accumulator circuits of the first plurality of MAC pipeline.

21. The integrated circuit of claim 17 wherein: each logic tile of the plurality of logic tiles includes a switch interconnect network, coupled between the configurable interface circuitry and the first and second memories, wherein the switch interconnect network includes a plurality of configurable multiplexers arranged in a plurality of switch matrices to: connect the first plurality of MAC pipelines to the first and second memories, via the configurable interface circuitry, during performance of the first data processing operations, and connect the second plurality of MAC pipelines to the first and second memories, via the configurable interface circuitry, during performance of the second data processing operations.

22. The integrated circuit of claim 21 wherein: the plurality of switch matrices of the switch interconnect network of each logic tile are arranged in a plurality of switch matrix stages interconnected in a hierarchical interconnect network.

23. The integrated circuit of claim 21 wherein: the configurable multiplexers of the switch interconnect network of each logic tile are responsively configured, in situ, to connect the multiplier-accumulator circuits of the second plurality of MAC pipelines to the configurable interface circuitry during the second data processing operations.