Display Device, Power Supply Circuit and Power Supply Method

1. A power supply circuit for a display screen, comprising: a control sub-circuit, configured to provide a first preset voltage and a second preset voltage and output the first preset voltage to a first power supply terminal; and a delay sub-circuit, configured to delay the second preset voltage and output the delayed second preset voltage to a second power supply terminal during a powering process for the display screen, wherein the control sub-circuit is a power chip; wherein the power chip comprises a first output terminal and a second output terminal, the first output terminal is configured to provide the first preset voltage, and the second output is configured to provide the second preset voltage, wherein the first output terminal is used as the first power supply terminal; and wherein the delay sub-circuit comprises an input terminal and an output terminal, the input terminal is connected to the second output terminal of the power chip, the output terminal of the delay sub-circuit is connected to the second power supply terminal to delay the second preset voltage provided by the power chip and output the delayed second preset voltage to the second power supply terminal, wherein the first power supply terminal is connected to a first power receiving terminal of a the display screen, and the second power supply terminal is connected to a second power receiving terminal of the display screen.

2. The power supply circuit according to claim 1 , wherein the delay sub-circuit comprises: a first switch transistor, wherein a control terminal of the first switch transistor is connected to the input terminal of the delay sub-circuit, and a first terminal of the first switch transistor is grounded; a second switch transistor, wherein a first terminal of the second switch transistor is connected to the input terminal of the delay sub-circuit, and a second terminal of the second switch transistor is connected to the output terminal of the delay sub-circuit; and a voltage division and delay sub-circuit, wherein a first terminal of the voltage division and delay sub-circuit is connected to the input terminal of the delay sub-circuit, and a second terminal of the voltage division and delay sub-circuit is connected to the second terminal of the first switch transistor, a voltage division terminal of the voltage division and delay sub-circuit is connected to a control terminal of the second switch transistor, and a delay terminal of the voltage division and delay sub-circuit is connected to the output terminal of the delay sub-circuit after the delay terminal of the voltage division and delay sub-circuit is connected to the second terminal of the second switch transistor.

3. The power supply circuit according to claim 2 , wherein the first switch transistor is an NMOS transistor, and the second switch transistor is a PMOS transistor.

4. The power supply circuit according to claim 2 , wherein where the second preset voltage provided by the control sub-circuit is input to the input terminal of the delay sub-circuit, the first switch transistor is turned on under driving of the second preset voltage; the voltage division and delay sub-circuit is configured to divide the second preset voltage provided by the power chip, after the first switch transistor is turned on, to generate a divided voltage signal and output the divided voltage signal through the voltage division terminal to the second switch transistor to drive the second switch transistor to be turned on; after the second switch is turned on, the second preset voltage is delayed to be output.

5. The power supply circuit according to claim 2 , wherein the voltage division and delay sub-circuit comprises: a first resistor, wherein a first terminal of the first resistor is used as the second terminal of the voltage division and delay sub-circuit, and a second terminal of the first resistor is connected to the voltage division terminal of the voltage division and delay sub-circuit; and a second resistor, wherein a first terminal of the second resistor is used as the first terminal of the voltage division and delay sub-circuit, and a second terminal of the second resistor is connected to the voltage division terminal of the voltage division and delay sub-circuit.

6. The power supply circuit according to claim 5 , wherein the voltage division and delay sub-circuit further comprises: a first capacitor, wherein a first terminal of the first capacitor is connected to the voltage division terminal of the voltage division and delay sub-circuit, and a second terminal of the first capacitor is used as the delay terminal of the voltage division and delay sub-circuit.

7. The power supply circuit according to claim 5 , wherein the voltage division and delay sub-circuit further comprises: a second capacitor, wherein a first terminal of the second capacitor is connected to the first terminal of the second resistor, and a second terminal of the second capacitor is connected to the second terminal of the second resistor.

8. The power supply circuit according to claim 6 , wherein a preset delay time period of the delay sub-circuit is R 1 *C 1 *Ln ((ELVDD_IN−ELVDD_OUT)/ELVDD_IN), where R 1 is a resistance value of the first resistor, C 1 is a capacitance value of the second capacitor, ELVDD_IN is a voltage of the input terminal of the delay sub-circuit, ELVDD_OUT is a voltage of the output terminal of the delay sub-circuit, and Ln is a natural logarithm.

9. A display device, comprising the power supply circuit according to claim 1 .

10. A power supply method for a display screen, comprising: outputting a first preset voltage provided by a control sub-circuit to a first power supply terminal; and delaying a second preset voltage provided by the control sub-circuit by a delay sub-circuit, and outputting the delayed second preset voltage to a second power supply terminal during a powering process of the display screen, wherein the control sub-circuit is a power chip; wherein the first preset voltage is provided by a first output terminal of the power chip, and the first preset voltage provided by the power chip is output to the first power supply terminal; wherein the second preset voltage is provided by a second output terminal of the power chip, the second preset voltage is delayed to be output, and the delayed second output voltage is output to the second power supply terminal.

11. The power supply method according to claim 10 , wherein the delay sub-circuit comprises a first switch transistor and a second switch transistor, and delaying the second preset voltage provided by the control sub-circuit by the delay sub-circuit comprises: acquiring the second preset voltage provided by the control sub-circuit, wherein the first switch transistor is turned on under driving of the second preset voltage; after the first switch transistor is turned on, the second preset voltage provided by the power chip is divided to generate a divided voltage signal, wherein the second switch transistor is turned on under driving of the divided voltage signal; and after the second switch transistor is turned on, the second preset voltage is delayed to be output.

12. The power supply circuit according to claim 3 , wherein where the second preset voltage provided by the control sub-circuit is input to the input terminal of the delay sub-circuit, the first switch transistor is turned on under driving of the second preset voltage; the voltage division and delay sub-circuit is configured to divide the second preset voltage provided by the power chip, after the first switch transistor is turned on, to generate a divided voltage signal and output the divided voltage signal through the voltage division terminal to the second switch transistor to drive the second switch transistor to be turned on; after the second switch is turned on, the second preset voltage is delayed to be output.

13. The power supply circuit according to claim 3 , wherein the voltage division and delay sub-circuit comprises: a first resistor, wherein a first terminal of the first resistor is used as the second terminal of the voltage division and delay sub-circuit, and a second terminal of the first resistor is connected to the voltage division terminal of the voltage division and delay sub-circuit; and a second resistor, wherein a first terminal of the second resistor is used as the first terminal of the voltage division and delay sub-circuit, and a second terminal of the second resistor is connected to the voltage division terminal of the voltage division and delay sub-circuit.

14. The power supply circuit according to claim 13 , wherein the voltage division and delay sub-circuit further comprises: a first capacitor, wherein a first terminal of the first capacitor is connected to the voltage division terminal of the voltage division and delay sub-circuit, and a second terminal of the first capacitor is used as the delay terminal of the voltage division and delay sub-circuit.

15. The power supply circuit according to claim 13 , wherein the voltage division and delay sub-circuit further comprises: a second capacitor, wherein a first terminal of the second capacitor is connected to the first terminal of the second resistor, and a second terminal of the second capacitor is connected to the second terminal of the second resistor.

16. The power supply circuit according to claim 4 , wherein the voltage division and delay sub-circuit comprises: a first resistor, wherein a first terminal of the first resistor is used as the second terminal of the voltage division and delay sub-circuit, and a second terminal of the first resistor is connected to the voltage division terminal of the voltage division and delay sub-circuit; and a second resistor, wherein a first terminal of the second resistor is used as the first terminal of the voltage division and delay sub-circuit, and a second terminal of the second resistor is connected to the voltage division terminal of the voltage division and delay sub-circuit.

17. The power supply circuit according to claim 16 , wherein the voltage division and delay sub-circuit further comprises: a first capacitor, wherein a first terminal of the first capacitor is connected to the voltage division terminal of the voltage division and delay sub-circuit, and a second terminal of the first capacitor is used as the delay terminal of the voltage division and delay sub-circuit.

18. The power supply circuit according to claim 16 , wherein the voltage division and delay sub-circuit further comprises: a second capacitor, wherein a first terminal of the second capacitor is connected to the first terminal of the second resistor, and a second terminal of the second capacitor is connected to the second terminal of the second resistor.