Variable-Length Clock Stretcher with Correction for Digital DLL Glitches

1. A method to correct glitches due to delay line speed changes in a clock stretcher, wherein the clock stretcher receives input clock pulses on an input and delivers pulses of a modified clock on an output, the method comprising the following steps: delaying the input clock pulses in a delay line including delay stages in a DLL; receiving a required length value N1 that may be changed in runtime; determining an end-of-chain (EOC) value for an input clock pulse traveling through the delay line; in the DLL, locking a delay of N1 delay stages to clock cycle time T and forwarding N1 phases of the delayed input clock pulses to a combiner; cyclically selecting and coupling at least one of the N1 phases with the clock stretcher output to obtain the modified clock; monitoring if a delay line speed change occurs; upon determining that no delay line speed change occurs, using a standard hop code to calculate an output phase selection for a duration of one input clock pulse, wherein the standard hop code is dependent on a sensed condition; and upon determining that a delay line speed change occurs, using an increased hop code to calculate the output phase selection for the duration of the one input clock pulse, wherein the increased hop code is larger than the standard hop code.

2. The method of claim 1 , wherein the monitoring if a delay line speed change occurs includes monitoring an occurrence of a DLL internal clock active edge.

3. The method of claim 2 , wherein the sensed power supply powers the DLL without intervening voltage regulation.

4. The method of claim 1 , wherein the monitoring if a delay line speed change occurs includes monitoring if a change occurs in a DLL loop filter output signal.

5. The method of claim 4 , wherein the monitoring if a delay line speed change occurs includes determining if the change in the DLL loop filter output signal causes the delay line to slow down.

6. The method of claim 1 , wherein the sensed condition includes a sensed power supply voltage.

7. A clock stretcher comprising: a clock input configured for receiving an input clock; a required length input configured for receiving a parameter N1; a delay-locked loop (DLL) including a delay line with two or more delay stages, wherein: a delay line input is electrically coupled with the clock input; a DLL phase comparator and a DLL loop filter operate at a speed slower than the input clock; the DLL is operable to lock a delay of an active part of the delay line to a duration of a cycle of the input clock; and the active part of the delay line has a length of N1 delay stages; an end-of-chain (EOC) detector, operable to detect a clock signal pulse edge present on at least a part of the delay stages, and to provide an EOC number associated with a delay stage in which the clock pulse edge is detected, wherein the EOC detector is clocked by a version of the input clock; a control unit operable to: receive the parameter N1, a hop code h, an increased hop code ih, and DLL information; output a combiner control signal including a combiner address based on a cyclical selection of N1 delay line phase output signals, wherein the cyclical selection progresses based on N1, the hop code h, the increased hop code ih, and the DLL information; and a combiner operable to select at least one of the N1 delay line phase output signals based on the combiner address, and to forward the at least one of the N1 delay line phase output signals to a modified clock output.

8. The clock stretcher of claim 7 , wherein a cyclical selection progress is based on the parameter N1 and the hop code h when the DLL information indicates that a change in delay line speed occurs, and wherein the cyclical selection progress is based on the parameter N1 and the increased hop code ih when the DLL information indicates that no change in delay line speed occurs.

9. The clock stretcher of claim 7 , wherein the DLL information includes an occurrence of a DLL internal clock active edge.

10. The clock stretcher of claim 7 , wherein the DLL information includes a DLL loop filter output signal, and wherein the control unit is operable to monitor whether a change occurs in the DLL loop filter output signal.

11. The clock stretcher of claim 7 , wherein the DLL information includes a change in a DLL loop filter output signal.

12. The clock stretcher of claim 7 , wherein the control unit is operable to monitor whether a change in a DLL loop filter output signal causes the delay line to slow down.

13. The clock stretcher of claim 7 , wherein the hop code h depends on a sensed condition.

14. The clock stretcher of claim 13 , wherein the sensed condition includes a voltage level.

15. The clock stretcher of claim 7 , wherein: the clock stretcher delivers a modified clock to a clocked system powered by a power supply; and the DLL is powered by the power supply without intervening voltage regulators.

16. The clock stretcher of claim 7 , wherein the EOC detector includes a series of phase detectors electrically coupled with the at least a part of the delay stages.

17. The clock stretcher of claim 7 , wherein the EOC detector includes a series of clocked comparators with inputs that are electrically coupled with the at least a part of the delay stages and with outputs electrically coupled with combinatorial logic to detect the clock signal pulse edge, wherein the combinatorial logic outputs the EOC number.

18. A clock stretcher circuit, comprising: a delay locked loop (DLL), having a delay line with a plurality of stages and phase detectors connected to at least a part of the stages in the plurality of stages, to lock the delay line in response to a phase error signal, and a circuit to calculate the phase error signal as a difference between a target active length N1 of the delay line and an actual length EOC; a first circuit to generate a DLL change signal when a DLL delay code to control a speed of the delay line stages changes; a voltage detector which generates a first control signal (hop count) in response to a sensed supply voltage; a control circuit connected to the phase detectors, to output a second control signal including the DLL change signal, wherein the control circuit includes the first circuit; and a clock combiner circuit, having inputs connected to outputs of the plurality of stages of the DLL and to the control circuit, to generate spaced out output clock pulses in dependence on the first and second control signals.