Clock Duty Cycle Adjustment and Calibration Circuit and Method of Operating Same

1. A clock circuit comprising: a set of level shifters configured to output a first set of phase clock signals having a first duty cycle, each level shifter of the set of level shifters being configured to output a corresponding phase clock signal of the first set of phase clock signals; a duty cycle adjustment circuit coupled to the set of level shifters, and configured to: generate a first clock output signal responsive to a first phase clock signal of the first set of phase clock signals, a second phase clock signal of the first set of phase clock signals and a set of control signals, the first clock output signal having a second duty cycle different from the first duty cycle, and adjust at least the second duty cycle responsive to at least the set of control signals or a phase difference between the first phase clock signal and the second phase clock signal; and a calibration circuit coupled to the duty cycle adjustment circuit, and configured to perform a duty cycle calibration of the second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.

2. The clock circuit of claim 1 , wherein the duty cycle adjustment circuit comprises: an adjustable delay circuit coupled to a first level shifter of the set of level shifters, and configured to output an adjusted first phase clock signal or the first phase clock signal of the first set of phase clock signals responsive to the first phase clock signal of the first set of phase clock signals and the set of control signals.

3. The clock circuit of claim 2 , wherein the duty cycle adjustment circuit further comprises: a multiplexer coupled to at least a sub-set of level shifters of the set of level shifters, the multiplexer being configured to: receive a sub-set of phase clock signals of the first set of phase clock signals from a corresponding level shifter of the sub-set of level shifters of the set of level shifters, and a select control signal, and output the second phase clock signal of the first set of phase clock signals, the second phase clock signal of the first set of phase clock signals being selected by the multiplexer from the sub-set of phase clock signals of the first set of phase clock signals in response to the select control signal, each phase clock signal of the sub-set of phase clock signals of the first set of phase clock signals having a corresponding phase.

4. The clock circuit of claim 3 , wherein the duty cycle adjustment circuit further comprises: an edge-triggered flip-flop comprising: a first NOR logic gate having a first output terminal configured to output the first clock output signal and being coupled to the calibration circuit, a first input terminal coupled to the multiplexer and being configured to receive the second phase clock signal of the first set of phase clock signals, and a second input terminal; and a second NOR logic gate having a first output terminal configured to output an inverted first clock output signal and coupled to the second input terminal of the first NOR logic gate, a first input terminal coupled to the adjustable delay circuit, and being configured to receive the adjusted first phase clock signal or the first phase clock signal of the first set of phase clock signals, and a second input terminal coupled to the first output terminal of the first NOR logic gate and being configured to receive the first clock output signal.

5. The clock circuit of claim 1 , wherein the calibration circuit comprises: a programmable duty reference generator circuit configured to receive the input duty cycle, and to generate a duty cycle reference signal responsive to the input duty cycle; a scrambler circuit coupled to the programmable duty reference generator circuit, and configured to generate a scrambled duty cycle signal responsive to the duty cycle reference signal; a first filter coupled to the scrambler circuit, and configured to generate a filtered scrambled duty cycle signal responsive to the scrambled duty cycle signal; a second filter coupled to the duty cycle adjustment circuit, and configured to generate a filtered first clock output signal responsive to the first clock output signal; a comparator coupled to the first filter and the second filter, and configured to generate a comparison signal based on a comparison of the filtered scrambled duty cycle signal and the filtered first clock output signal; and a controller coupled to the comparator and the duty cycle adjustment circuit, and configured to generate the set of control signals responsive to the comparison signal.

6. The clock circuit of claim 1 , further comprising: a clock generating circuit coupled to the set of level shifters, the clock generating circuit having a set of stages, and being configured to generate a second set of phase clock signals having the first duty cycle, each stage of the set of stages of the clock circuit being configured to output a corresponding phase clock signal of the second set of phase clock signals to a corresponding level shifter of the set of level shifters, wherein each level shifter is configured to output the corresponding phase clock signal of the first set of phase clock signals based on the corresponding phase clock signal of the second set of phase clock signals.

7. The clock circuit of claim 6 , wherein the clock generating circuit comprises a ring oscillator, the ring oscillator comprising: a first set of inverters coupled to each other in a ring, wherein an output terminal of a first inverter on a first end is coupled to an input terminal of a second inverter on an opposite end from the first end, each inverter of the first set of inverters corresponds to the stage of the set of stages, and a number of stages of the set of stages being odd; a second set of inverters, each inverter of the second set of inverters being coupled to a corresponding pair of inverters of the first set of inverters and a corresponding level shifter of the set of level shifters; and a set of buffers, each buffer of the set of buffers being coupled to another corresponding pair of inverters of the first set of inverters and another corresponding level shifter of the set of level shifters.

8. A clock duty cycle adjustment and calibration circuit comprising: a clock circuit having a set of stages, the clock circuit configured to generate a first set of phase clock signals having a first duty cycle; a set of level shifters coupled to the clock circuit, and configured to output a second set of phase clock signals, each level shifter being coupled to a corresponding stage of the set of stages of the clock circuit, each level shifter configured to output a corresponding phase clock signal of the second set of phase clock signals based on a corresponding phase clock signal of the first set of phase clock signals; a duty cycle adjustment circuit coupled to the set of level shifters, and configured to: generate a first clock output signal responsive to a first phase clock signal of the second set of phase clock signals, a second phase clock signal of the second set of phase clock signals, and a set of control signals, the first clock output signal having a duty cycle, and adjust at least the duty cycle responsive to at least the set of control signals or a phase difference between the first phase clock signal of the second set of phase clock signals and the second phase clock signal of the second set of phase clock signals; and a duty cycle calibration circuit coupled to the duty cycle adjustment circuit, and configured to perform a calibration of the duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the calibration of the duty cycle of the first clock output signal.

9. The clock duty cycle adjustment and calibration circuit of claim 8 , wherein the duty cycle adjustment circuit comprises: a multiplexer coupled to a sub-set of level shifters of the set of level shifters, the multiplexer being configured to receive a sub-set of phase clock signals of the second set of phase clock signals from a corresponding sub-set of level shifters of the set of level shifters, and a select control signal, and being configured to output the second phase clock signal of the second set of phase clock signals, the second phase clock signal of the second set of phase clock signals being selected by the multiplexer from the sub-set of phase clock signals of the second set of phase clock signals in response to the select control signal, each phase clock signal of the sub-set of phase clock signals of the second set of phase clock signals having a corresponding phase.

10. The clock duty cycle adjustment and calibration circuit of claim 9 , wherein the duty cycle adjustment circuit further comprises: an adjustable delay circuit coupled to a first level shifter of the set of level shifters, and configured to output an adjusted first phase clock signal or the first phase clock signal of the second set of phase clock signals responsive to the first phase clock signal of the second set of phase clock signals and the set of control signals; and an edge triggered flip-flop coupled to the multiplexer and the adjustable delay circuit, and configured to output the first clock output signal responsive to the adjusted first phase clock signal or the first phase clock signal of the second set of phase clock signals, and the second phase clock signal of the second set of phase clock signals.

11. The clock duty cycle adjustment and calibration circuit of claim 10 , wherein the edge triggered flip-flop comprises: an SR flip-flop comprising: a first NOR logic gate having a first output terminal configured to output the first clock output signal and being coupled to the duty cycle calibration circuit, a first input terminal coupled to the multiplexer and being configured to receive the second phase clock signal of the second set of phase clock signals, and a second input terminal; and a second NOR logic gate having a first output terminal configured to output an inverted first clock output signal and coupled to the second input terminal of the first NOR logic gate, a first input terminal coupled to the adjustable delay circuit and being configured to receive the adjusted first phase clock signal or the first phase clock signal of the second set of phase clock signals, and a second input terminal coupled to the first output terminal of the first NOR logic gate and being configured to receive the first clock output signal.

12. The clock duty cycle adjustment and calibration circuit of claim 11 , wherein the duty cycle calibration circuit comprises: a programmable duty reference generator circuit configured to receive the input duty cycle, and to generate a duty cycle reference signal responsive to the input duty cycle; a scrambler circuit coupled to the programmable duty reference generator circuit, and configured to generate a scrambled duty cycle signal responsive to the duty cycle reference signal; a first filter coupled to the scrambler circuit, and configured to generate a filtered scrambled duty cycle signal responsive to the scrambled duty cycle signal; a second filter coupled to the first output terminal of the first NOR logic gate, and configured to generate a filtered first clock output signal responsive to the first clock output signal; a comparator coupled to the first filter and the second filter, and configured to generate a comparison signal based on a comparison of the filtered scrambled duty cycle signal and the filtered first clock output signal; and a controller coupled to the comparator and the delay adjustment circuit, and configured to generate the set of control signals responsive to the comparison signal.

13. The clock duty cycle adjustment and calibration circuit of claim 12 , wherein the first filter comprises: a first low pass filter including a first capacitor and a first resistor; and the second filter comprises: a second low pass filter including a second capacitor and a second resistor; the first capacitor has a first capacitance, the second capacitor has a second capacitance equal to the first capacitance, the first resistor has a first resistance, and the second resistor has a second resistance equal to the first resistance.

14. The clock duty cycle adjustment and calibration circuit of claim 8 , wherein the clock circuit comprises: a differential ring oscillator having an even number of stages of the set of stages; and a first set of inverters, each inverter of the first set of inverters being coupled to a corresponding stage of the set of stages of the differential ring oscillator and a corresponding level shifter of the set of level shifters.

15. The clock duty cycle adjustment and calibration circuit of claim 14 , wherein the differential ring oscillator comprises: a second set of inverters in a first path having a first end and a second end opposite from the first end, each inverter of the second set of inverters corresponds to the stage of the set of stages; a third set of inverters in a second path having a third end and a fourth end opposite from the third end, the second end being coupled to the third end, and the fourth end being coupled to the first end, each inverter of the third set of inverters corresponds to the stage of the set of stages; and a set of latches, each latch of the set of latches being coupled between the first path and the second path, each latch of the set of latches corresponds to the stage of the set of stages.

16. A method of operating a clock duty cycle adjustment and calibration circuit, the method comprising: generating, by a set of level shifters, a first set of phase clock signals having a first duty cycle, each phase clock signal of the first set of phase clock signals being generated by a corresponding level shifter of the set of level shifters; generating, by a duty cycle adjustment circuit, a first clock output signal responsive to a first phase clock signal of the first set of phase clock signals and a second phase clock signal of the first set of phase clock signals, the first clock output signal having a second duty cycle; and calibrating, by a duty cycle calibration circuit, the second duty cycle of the first clock output signal based on at least an input duty cycle, the duty cycle calibration circuit being coupled to the duty cycle adjustment circuit.

17. The method of claim 16 , further comprising: adjusting, by the duty cycle adjustment circuit, the first clock output signal responsive to at least a set of control signals, thereby generating an adjusted first clock output signal having an adjusted second duty cycle.

18. The method of claim 17 , wherein adjusting the first clock output signal comprises: adjusting, by the duty cycle adjustment circuit, the first phase clock signal of the first set of phase clock signals responsive to at least the set of control signals, thereby generating an adjusted first phase clock signal of the first set of phase clock signals; receiving the adjusted first phase clock signal of the first set of phase clock signals as a first input to an edge triggered circuit; selecting, by a multiplexer, the second phase clock signal of the first set of phase clock signals as a second input to the edge triggered circuit; receiving the second phase clock signal of the first set of phase clock signals as the second input to the edge triggered circuit; and generating, by the edge triggered circuit, the adjusted first clock output signal responsive to the adjusted first phase clock signal of the first set of phase clock signals and the second phase clock signal of the first set of phase clock signals.

19. The method of claim 17 , wherein calibrating the second duty cycle of the first clock output signal based on the input duty cycle comprises: receiving the input duty cycle from a user; generating, by a programmable duty reference generator circuit, a duty cycle reference signal responsive to the input duty cycle; generating, by a scrambler circuit, a scrambled duty cycle signal responsive to the duty cycle reference signal, the scrambler circuit being coupled to the programmable duty reference generator circuit; generating, by a first filter, a filtered scrambled duty cycle signal responsive to the scrambled duty cycle signal, the first filter being coupled to the scrambler circuit; generating, by a second filter, a filtered first clock output signal responsive to the first clock output signal or the adjusted first clock output signal, the second filter being coupled to an edge triggered circuit; generating, by a comparator, a comparison signal based on a comparison of the filtered scrambled duty cycle signal and the filtered first clock output signal, the comparator being coupled to the first filter and the second filter; and generating, by a controller, the set of control signals responsive to the comparison signal, the controller being coupled to the comparator and a delay adjustment circuit.

20. The method of claim 16 , wherein generating the first clock output signal comprises: receiving the first phase clock signal of the first set of phase clock signals as a first input to an edge triggered circuit; selecting, by a multiplexer, the second phase clock signal of the first set of phase clock signals as a second input to the edge triggered circuit; and receiving the second phase clock signal of the first set of phase clock signals as the second input to the edge triggered circuit.