Processing of Plural-Register-Load Instruction

1. An apparatus comprising: processing circuitry to issue load operations to load data from memory, where in response to a plural-register-load instruction specifying a plurality of destination registers to be loaded with data from respective target addresses, the processing circuitry is configured to permit a plurality of load operations corresponding to the plural-register-load instruction to be issued as separate load operations; and load tracking circuitry configured to maintain tracking information for one or more issued load operations; in which: when the plural-register-load instruction is subject to an atomicity requirement and the plurality of load operations are issued as separate load operations, the load tracking circuitry is configured to: detect, based on the tracking information, whether a loss-of-atomicity condition has occurred for the plurality of load operations corresponding to the plural-register-load instruction, the loss-of-atomicity condition comprising a condition indicative of a risk that, between processing of an earlier processed load operation and processing of a later processed load operation of the plurality of load operations, data associated with an address of the earlier processed load operation has changed; and request re-processing of the plural-register-load instruction when the loss-of-atomicity condition is detected; wherein the load tracking circuitry is configured to detect occurrence of the loss-of-atomicity condition when a coherency snoop request specifying a snoop address corresponding to the address of the earlier processed load operation is detected between processing of the earlier processed load operation and processing of the later processed load operation.

2. The apparatus according to claim 1 , comprising an atomicity data buffer; in which: the processing circuitry is configured to support an atomicity-buffering-mode of processing the plurality of load operations corresponding to the plural-register-load instruction; and when the plurality of load operations are issued as separate load operations and processed in the atomicity-buffering mode: in response to the earlier processed load operation, the processing circuitry is configured to load at least one data word which comprises a first portion required for processing of the earlier processed load operation and a second portion required for processing of the later processed load operation, and to allocate the second portion into the atomicity data buffer; and in response to the later processed load operation which requires the second portion, the processing circuitry is configured to obtain the second portion from the atomicity data buffer.

3. The apparatus according to claim 2 , in which the processing circuitry is configured to process the plurality of load operations corresponding to the plural-register-load instruction in the atomicity-buffering mode when the plurality of load operations include an oldest pending load operation remaining to be processed.

4. The apparatus according to claim 1 , in which the respective target addresses for the plural-register-load instruction are addresses of contiguous blocks of address space.

5. The apparatus according to claim 1 , in which the processing circuitry is configured to support: a cracked mode of processing the plural-register-load instruction, in which the processing circuitry is configured to crack the plural-register-load instruction into the plurality of load operations to be issued as separate load operations; and a non-cracked mode of processing the plural-register load instruction, in which the processing circuitry is configured to: issue, in response to the plural-register-load instruction, a single load operation to load a combined block of data, the combined block of data including portions of data to be loaded to each of the destination registers of the plural-register load instruction; and allocate a plurality of load-data-returning paths for use in response to the single load operation, each of the plurality of load-data-returning paths allocated for returning the data required to be loaded to a respective one of the destination registers.

6. The apparatus according to claim 5 , comprising counting circuitry to: count a number of occurrences of the loss-of-atomicity condition when the processing circuitry is in the cracked mode, and request that the processing circuitry switches to the non-cracked mode when the number of occurrences of the loss-of-atomicity condition exceeds or reaches a predetermined threshold.

7. The apparatus according to claim 1 , in which in response to a synchronisation request requesting confirmation that a predetermined event has occurred, the processing circuitry is configured to provide a synchronisation response when the predetermined event has occurred; and when the synchronisation request is received between processing of the earlier processed load operation and processing of the later processed load operation, the processing circuitry is configured to defer providing the synchronisation response until after the later processed load operation has been processed.

8. The apparatus according to claim 1 , in which the plural-register-load instruction is a load-pair instruction for which the number of destination registers is 2.

9. The apparatus according to claim 1 , in which the processing circuitry comprises N load pipelines to process load operations in parallel, where N is an odd integer greater than or equal to 3.

10. An apparatus comprising: processing circuitry to issue load operations to load data from memory, where in response to a plural-register-load instruction specifying a plurality of destination registers to be loaded with data from respective target addresses, the processing circuitry is configured to permit a plurality of load operations corresponding to the plural-register-load instruction to be issued as separate load operations; and load tracking circuitry configured to maintain tracking information for one or more issued load operations; in which: when the plural-register-load instruction is subject to an atomicity requirement and the plurality of load operations are issued as separate load operations, the load tracking circuitry is configured to: detect, based on the tracking information, whether a loss-of-atomicity condition has occurred for the plurality of load operations corresponding to the plural-register-load instruction, the loss-of-atomicity condition comprising a condition indicative of a risk that, between processing of an earlier processed load operation and processing of a later processed load operation of the plurality of load operations, data associated with an address of the earlier processed load operation has changed; and request re-processing of the plural-register-load instruction when the loss-of-atomicity condition is detected; wherein the load tracking circuitry is configured to maintain, as the tracking information, a tracking structure comprising one or more tracking entries, each tracking entry specifying at least: an instruction identifier associated with a processed load operation; an address of the processed load operation; and a hazard indication indicative of whether a hazard condition has been detected for the processed load operation.

11. The apparatus according to claim 10 , in which when the plural-register-load instruction is processed with the plurality of load operations issued as separate load operations, the processing circuitry is configured to allocate the same instruction identifier to each of the plurality of load operations corresponding to the plural-register-load instruction.

12. The apparatus according to claim 10 , in which the load tracking circuitry is configured to allocate a tracking entry in the tracking structure for a given load operation corresponding to the plural-register-load instruction, in response to processing of the given load operation.

13. The apparatus according to claim 10 , in which the load tracking circuitry is configured to set the hazard indication for a given tracking entry of the tracking structure to indicate that the hazard condition has been detected, in response to detecting a coherency snoop request specifying a snoop address corresponding to the address specified by the given tracking entry.

14. The apparatus according to claim 10 , in which in response to processing of a given load operation corresponding to the plural-register-load instruction associated with a given instruction identifier, the load tracking circuitry is configured to detect occurrence of the loss-of-atomicity condition when the tracking structure is detected as already including a tracking entry specifying said given instruction identifier for which the hazard indication indicates that the hazard condition has been detected.

15. The apparatus according to claim 14 , in which in response to detecting the loss-of-atomicity condition, the load tracking circuitry is configured to request that the processing circuitry re-processes at least a given plural-register-load instruction identified by the given instruction identifier associated with the given load operation which caused the loss-of-atomicity condition to be detected and one or more subsequent instructions younger than the given plural-register-load instruction.

16. The apparatus according to claim 10 , in which the load tracking circuitry is also configured to use the tracking information to determine: whether at least one load operation has been issued in disagreement with a memory ordering requirement; and when it is determined that the at least one load operation has been issued in disagreement with the memory ordering requirement, whether to re-issue one or more issued load operations or to continue issuing load operations despite disagreement with the memory ordering requirement.

17. The apparatus according to claim 10 , in which in response to processing of a given load operation associated with a given instruction identifier identifying a given instruction, the load tracking circuitry is configured to detect a memory ordering violation when the tracking structure includes a hazarding entry for which: the instruction identifier specified by the hazarding entry corresponds to a younger instruction than the given instruction; an address specified by the hazarding entry corresponds to an address of the given load operation; and the hazard indication specified by the hazarding entry indicates that the hazard condition has been detected.

18. The apparatus according to claim 17 , in which in response to detecting the memory ordering violation, the load tracking circuitry is configured to request that the processing circuitry re-processes at least the younger instruction identified by the instruction identifier specified by the hazarding entry and one or more subsequent instructions younger than the younger instruction, and to permit processing to continue without re-issuing the given instruction.

19. A data processing method comprising: in response to a plural-register-load instruction specifying a plurality of destination registers to be loaded with data from respective target addresses, issuing a plurality of load operations corresponding to the plural-register-load instruction, using processing circuitry which permits the plurality of load operations to be issued as separate load operations; and maintaining tracking information for one or more issued load operations; in which: when the plural-register-load instruction is subject to an atomicity requirement and the plurality of load operations are issued as separate load operations, the method comprises: detecting, based on the tracking information, whether a loss-of-atomicity condition has occurred for the plurality of load operations corresponding to the plural-register-load instruction, the loss-of-atomicity condition comprising a condition indicative of a risk that, between processing of an earlier processed load operation and processing of a later processed load operation of the plurality of load operations, data associated with an address of the earlier processed load operation has changed; requesting re-processing of the plural-register-load instruction when the loss-of-atomicity condition is detected; and detecting an occurrence of the loss-of-atomicity condition when a coherency snoop request specifying a snoop address corresponding to the address of the earlier processed load operation is detected between processing of the earlier processed load operation and processing of the later processed load operation.