Method, Apparatus And System For Device Transparent Grouping Of Devices On A Bus

1. An apparatus comprising: a host controller to couple to an interconnect, the host controller including: a first input/output (I/O) buffer to couple to a first communication line of the interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to: dynamically cause the first communication line to communicate only a clock signal to a first device group including one or more first devices and dynamically cause the second communication line to communicate only a data signal to the first device group when a communication of a first protocol is addressed to at least one of the one or more first devices of the first device group; and dynamically cause the first communication line to communicate only a data signal to a second device group including one or more second devices and dynamically cause the second communication line to communicate only a clock signal to the second device group when a communication of the first protocol is addressed to at least one of the one or more second devices of the second device group.

2. The apparatus of claim 1 , wherein the host controller further comprises: a first selection circuit having a first input to receive the clock signal and a second input to receive the data signal, the device group selection circuit to control the first selection circuit to output the clock signal when the communication is to be addressed to the at least one of the one or more first devices; and a second selection circuit having a first input to receive the data signal and a second input to receive the clock signal, the device group selection circuit to control the second selection circuit to output the data signal when the communication is to be addressed to the at least one of the one or more first devices.

3. The apparatus of claim 2 , wherein the device group selection circuit is to output a select signal to control the first selection circuit and further comprising an inverter to receive the select signal and output an inverted select signal, wherein the inverted select signal is to control the second selection circuit.

4. The apparatus of claim 2 , wherein the first I/O buffer is coupled to an output of the first selection circuit and the second I/O buffer is coupled to an output of the second selection circuit.

5. The apparatus of claim 1 , wherein the one or more first devices include a clock receiver coupled to the first I/O buffer and the one or more second devices include a data receiver coupled to the first I/O buffer.

6. The apparatus of claim 5 , wherein the one or more first devices include a data receiver coupled to the second I/O buffer and the one or more second devices include a clock receiver coupled to the second I/O buffer.

7. The apparatus of claim 1 , wherein the host controller is to communicate with a first device of the one or more first devices using a first address and communicate with a second device of the one or more second devices using the first address.

8. The apparatus of claim 1 , wherein when the communication is to be addressed to the at least one of the one or more first devices of the first device group, the communication is to be transparent to the second device group.

9. The apparatus of claim 1 , wherein the host controller is to send a first reset pattern to the first device group and thereafter send a second reset pattern to the second device group.

10. A system comprising: a host controller having a first input/output (I/O) buffer coupled to a first communication line and a second I/O buffer coupled to a second communication line; a first device group including one or more first devices coupled to the host controller, wherein each of the one or more first devices includes a clock buffer to receive only a clock signal sent by the host controller on the first communication line and a data buffer to receive only a data signal sent by the host controller on the second communication line; and a second device group including one or more second devices coupled to the host controller, wherein each of the one or more second devices includes a data buffer to receive only a data signal sent by the host controller on the first communication line and a clock buffer to receive only a clock signal sent by the host controller on the second communication line.

11. The system of claim 10 , wherein the host controller is to address 2 N devices using N−1 address bits, wherein N is a positive number greater than 2.

12. The system of claim 10 , wherein a first device of the one or more first devices and a second device of the one or more second devices are identified with a same address.

13. The system of claim 10 , wherein the first device group comprises a first plurality of memory modules having or more first independently addressable devices and the second device group comprises a second plurality of memory modules having one or more second independently addressable devices, wherein one of the first independently addressable devices and one of the second independently addressable devices have a common address.

14. The system of claim 10 , wherein the host controller is to: cause the first I/O buffer to output the clock signal and cause the second I/O buffer to output the data signal for a first message, to enable at least one of the one or more first devices of the first device group to receive the first message, the first message transparent to the second device group; and cause the second I/O buffer to output the clock signal and cause the first I/O buffer to output the data signal for a second message, to enable at least one of the one or more second devices of the second device group to receive the second message, the second message transparent to the first device group.

15. An apparatus comprising: at least one core; and an interface circuit coupled to the at least one core, the interface circuit comprising: a first input/output (I/O) buffer to couple to a first communication line of a multi-drop bus; a second I/O buffer to couple to a second communication line of the multi-drop bus; and a selection circuit to: dynamically cause the first communication line to communicate only a clock signal to a first device group including one or more first memory devices and dynamically cause the second communication line to communicate only a data signal to the first device group when a communication of a first protocol is addressed to at least one of the one or more first memory devices of the first device group; and dynamically cause the first communication line to communicate only a data signal to a second device group including one or more second memory devices and dynamically cause the second communication line to communicate only a clock signal to the second device group when a communication of the first protocol is addressed to at least one of the one or more second devices of the second device group, wherein the second device group is coupled in opposition to the first device group.

16. The apparatus of claim 15 , wherein the multi-drop bus has an N-bit addressing scheme and greater than 2 N of a sum of the first memory devices and the second memory devices are present.

17. The apparatus of claim 16 , wherein a first bit of an address of the N-bit addressing scheme is to identify which of the first device group or the second device group the communication is to be directed.

18. The apparatus of claim 16 , wherein in response to the communication the host controller is to receive telemetry information from the at least one of the one or more first memory devices of the first device group.

19. The apparatus of claim 15 , wherein the first protocol comprises an I3C protocol.