Multi-Page Parity Protection with Power Loss Handling

1. A memory system comprising: multiple parity groups arranged for data protection of the memory system, the multiple parity groups including a parity group having multiple data pages in which to write data and having a parity page in which to write parity data generated from the data written in the multiple data pages, each data page of the multiple data pages of the parity group including: a metadata region for data written to the data page; and a flag region allocated in the metadata region to identify one or more other data pages with the one or more other data pages impacted by an asynchronous power loss event, the one or more other data pages preceding the data page in an order of writing data to the data pages of the parity group.

2. The memory system of claim 1 , wherein asynchronous power loss status of the one or more data pages includes an asynchronous power loss impacted status in which completion of a write operation of the data to a preceding data page in the order is prevented.

3. The memory system of claim 1 , comprising: a memory controller including processing circuitry having one or more processors, the memory controller configured to perform operations comprising, for each parity group, excluding data pages of the parity group, tagged as asynchronous power loss impacted, in a re-construction of data following an uncorrectable error correction code error in writing to a selected data page of the parity group.

4. The memory system of claim 1 , wherein a flag region of a given data page written as a first page in the parity group has a flag set to zero.

5. The memory system of claim 1 , wherein the multiple parity groups are arranged in sub-blocks of a memory device.

6. A memory system comprising: a memory controller including processing circuitry having one or more processors, the memory controller configured to perform operations comprising: writing data to multiple data pages of a parity group, the parity group including a parity page in which to write parity data generated from the data written in the multiple data pages; and controlling a flag region in metadata of each data page of the parity group in which the data is successfully written, the flag region arranged to include a flag to identify one or more other data pages with the one or more other data pages impacted by an asynchronous power loss event, the one or more other data pages preceding the data page in an order of writing data to the data pages of the parity group.

7. The memory system of claim 6 , wherein the flag is a byte of the metadata.

8. The memory system of claim 6 , wherein the flag in a given data page is a count of data pages of the parity group impacted by asynchronous power loss that preceded, in the order of writing data, the given data page of the parity group in which the data is successfully written.

9. The memory system of claim 6 , wherein the metadata of each data page of the parity group in which the data is successfully written includes a logical address for the data being stored in the data page.

10. The memory system of claim 6 , wherein the operations, for each parity group, include use of the flag to exclude one or more of the data pages of the parity group in a re-construction of data in a selected data page of the parity group in which an uncorrectable error correction code error occurred.

11. The memory system of claim 10 , wherein the re-construction starts by reading from a last data page of data written in the parity group.

12. The memory system of claim 6 , wherein the parity data is constructed by performing exclusive-or operations on the data written to the data pages followed by storing the parity data in the parity page of the parity group.

13. The memory system of claim 6 , wherein the order of writing data to the data pages of the parity group is defined by a numbering of access lines to the data pages, each data page of the parity group coupled to an access line different from the other data pages of the parity group.

14. A memory system comprising: multiple memory devices; and a memory controller including processing circuitry having one or more processors, the memory controller configured to perform operations comprising: identifying data pages among the multiple memory devices to form different parity groups with each parity group having multiple data pages; writing data to the multiple data pages of a parity group of the different parity groups, the parity group including a parity page in which to write parity data generated from the data written in the multiple data pages; and controlling a flag region in metadata of each data page of the parity group in which the data is successfully written, the flag region arranged to include a flag to identify one or more other data pages with the one or more other data pages impacted by an asynchronous power loss event, the one or more other data pages preceding the data page in an order of writing data to the data pages of the parity group.

15. The memory system of claim 14 , wherein the metadata of the data page includes one or more temperature readings.

16. The memory system of claim 15 , wherein the one or more temperature readings include a temperature at which the data is written in the data page.

17. The memory system of claim 14 , wherein the metadata of the data page includes a logical address for the data being stored in the data page.

18. The memory system of claim 14 , wherein controlling the flag region in the metadata of each data page of the parity group in which the data is successfully written includes setting a count of data pages of the parity group, impacted by asynchronous power loss, that preceded, in the order of writing data to the multiple data pages of the parity group, each data page in which the data is successfully written.

19. The memory system of claim 14 , wherein the memory controller is operable to: use the flag to exclude one or more of the data pages of the parity group impacted by asynchronous power loss in a re-construction of the data following an uncorrectable error correction code error in writing to a selected data page of the parity group; and start the re-construction by reading from a last data page of data written in the parity group.

20. The memory system of claim 14 , wherein at least one memory device of the multiple memory devices is arranged having multiple sub-blocks with each sub-block associated with a lower page, an upper page, and an extra page.