Shift Register Having Two Output Signals with Phase Lagging and Driving Method Thereof, Scan Driving Circuit, Display Panel and Display Device

1. A shift register, comprising: an input module, electrically connected to a signal input terminal and a first clock signal terminal, and configured to provide a signal of the signal input terminal to a first node in response to a signal of the first clock signal terminal; a control module, electrically connected to a first voltage terminal, a second clock signal terminal, and a second node, and configured to provide a voltage of the first voltage terminal to the first node in response to a voltage of the second node and a signal of the second clock signal terminal; a reset module, electrically connected to a second voltage terminal and the first clock signal terminal, and configured to provide a voltage of the second voltage terminal to the second node in response to the signal of the first clock signal terminal; a first output module, electrically connected to the first node and the second clock signal terminal, and configured to provide the signal of the second clock signal terminal to a first output terminal in response to a voltage of the first node; a second output module, electrically connected to the first node and a third clock signal terminal, and configured to provide a signal of the third clock signal terminal to a second output terminal in response to the voltage of the first node; and a stabilization module, electrically connected to the second node and the first voltage terminal, and configured to provide the voltage of the first voltage terminal to the first output terminal and the second output terminal respectively in response to the voltage of the second node, wherein: a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module, and the stabilization module includes: a first transistor, wherein a first terminal of the first transistor is electrically connected to the first voltage terminal, a second terminal of the first transistor is electrically connected to the first output terminal, and a control terminal of the first transistor is electrically connected to the second node; a second transistor, wherein a first terminal of the second transistor is electrically connected to the first voltage terminal, a second terminal of the second transistor is electrically connected to the second output terminal, and a control terminal of the second transistor is electrically connected to the second node; and a first capacitor, wherein a first plate of the first capacitor is electrically connected to the first voltage terminal, and a second plate of the first capacitor is electrically connected to the second node, the first output module includes: a third transistor, wherein a first terminal of the third transistor is electrically connected to the first output terminal, and a second terminal of the third transistor is electrically connected to the second clock signal terminal; and a second capacitor, wherein a first plate of the second capacitor is electrically connected to the first output terminal, and a second plate of the second capacitor is electrically connected to a control terminal of the third transistor; and the second output module includes: a fourth transistor, wherein a first terminal of the fourth transistor is electrically connected to the second output terminal, and a second terminal of the fourth transistor is electrically connected to the third clock signal terminal; and a third capacitor, wherein a first plate of the third capacitor is electrically connected to the second output terminal, and a second plate of the third capacitor is electrically connected to a control terminal of the fourth transistor, and a capacitance of the third capacitor is greater than a capacitance of the second capacitor.

2. The shift register according to claim 1 , wherein: a pulse width of the signal output from the second output module is equal to a pulse width of the signal output from the first output module.

3. The shift register according to claim 1 , wherein: 1.1<K<1.5, wherein K is a ratio of the capacitance of the third capacitor over the capacitance of the second capacitor.

4. The shift register according to claim 1 , wherein: the first output module further includes a fifth transistor, wherein a first terminal of the fifth transistor is electrically connected to the first node, a second terminal of the fifth transistor is electrically connected to the control terminal of the third transistor, and a control terminal of the fifth transistor is electrically connected to the second voltage terminal; and the second output module further includes a sixth transistor, wherein a first terminal of the sixth transistor is electrically connected to the first node, a second terminal of the sixth transistor is electrically connected to the control terminal of the fourth transistor, and a control terminal of the sixth transistor is electrically connected to the second voltage terminal.

5. The shift register according to claim 1 , wherein: an area where the third transistor is located is a first area, an area where the fourth transistor is located is a second area, the first area and the second area are arranged along a first direction, a size of the first area in the first direction is W1, a size of the first area in a second direction is L1, a size of the second area in the first direction is W2, and a size of the second area in the second direction is L2, wherein W1>W2, L1<L2; and the first direction intersects the second direction.

6. The shift register according to claim 5 , wherein: an area where the second capacitor is located is a third area, an area where the third capacitor is located is a fourth area, the third area and the fourth area are both L-shaped, the third area includes a first sub-area extending along the first direction and a second sub-area extending along the second direction, the fourth area includes a third sub-area extending in the first direction and a fourth sub-area extending in the second direction, the third area half-surrounds the first area, and the fourth area half-surrounds the second area.

7. The shift register according to claim 6 , wherein: a size of the first sub-area in the first direction is L3, a size of the second sub-area in the second direction is L4, a size of the third sub-area in the first direction is L5, and a size of the fourth sub-area in the second direction is L6, wherein |L1−L2|>|W1−W2|, |L4−L6|>|L3−L5|.

8. The shift register according to claim 1 , wherein: the first clock signal terminal provides a first clock signal, the second clock signal terminal provides a second clock signal, and the third clock signal terminal provides a third clock signal; and pulses of the first clock signal, the second clock signal, and the third clock signal do not overlap with each other, and are arranged sequentially in time.

9. The shift register according to claim 8 , wherein: a duty cycle of the first clock signal is greater than ¼ and less than or equal to ⅓.

10. The shift register according to claim 1 , wherein: the input module includes: a seventh transistor, wherein a first terminal of the seventh transistor is electrically connected to the signal input terminal, a second terminal of the seventh transistor is electrically connected to the first node, and a control terminal of the seventh transistor is electrically connected to the first clock signal terminal; and an eighth transistor, wherein a first terminal of the eighth transistor is electrically connected to the first clock signal terminal, a second terminal of the eighth transistor is electrically connected to the second node, and a control terminal of the eighth transistor is electrically connected to the first node; the control module includes: a ninth transistor, wherein a first terminal of the ninth transistor is electrically connected to the first voltage terminal, and a control terminal of the ninth transistor is electrically connected to the second node; and a tenth transistor, wherein a first terminal of the tenth transistor is electrically connected to a second terminal of the ninth transistor, a second terminal of the tenth transistor is electrically connected to the first node, and a control terminal of the tenth transistor is electrically connected to the second clock signal terminal; and the reset module includes: an eleventh transistor, wherein a first terminal of the eleventh transistor is electrically connected to the second voltage terminal, a second terminal of the eleventh transistor is electrically connected to the second node, and a control terminal of the eleventh transistor is electrically connected to the first clock signal terminal.

11. The shift register according to claim 1 , wherein: the input module provides a signal of the input signal terminal to the first node in response to a low level of the first clock signal terminal; the control module provides a first voltage of the first voltage terminal to the first node in response to a low level of the second clock signal terminal and a low level of the second node; the reset module provides a second voltage of the second voltage terminal to the second node in response to a low level of the first clock signal terminal; and the first voltage is greater than the second voltage.

12. The shift register according to claim 11 , wherein: the first output module provides a signal of the second clock signal terminal to the first output terminal in response to a first low level and a second low level of the first node; and the second output module provides a signal of the third clock signal terminal to the second output terminal at least in response to a third low level of the first node, wherein: the second low level is less than the first low level, and the third low level is less than the second low level.

13. A driving method of the shift register according to claim 1 , comprising: in a first stage, the signal input terminal inputs a low level, the first clock signal terminal inputs a low level, the second clock signal terminal inputs a high level, and the third clock signal terminal inputs a high level, configured to provide the low level input from the signal input terminal to the first node, and provide the low level input from the first clock signal terminal to the second node, so that the first output terminal and the second output terminal both output high levels; in a second stage, the signal input terminal inputs a high level, the first clock signal terminal inputs a high level, the second clock signal terminal inputs a low level, and the third clock signal terminal inputs a high level, configured to provide the high level input from the first clock signal terminal to the second node, so that the first output terminal outputs a low level, and the second output terminal outputs a high level; in a third stage, the signal input terminal inputs a high level, the first clock signal terminal inputs a high level, the second clock signal terminal inputs a high level, and the third clock signal terminal inputs a low level, configured to provide the high level input from the first clock signal terminal to the second node, so that the first output terminal outputs a high level, and the second output terminal outputs a low level; and in a fourth stage, the signal input terminal inputs a high level, the first clock signal terminal inputs a low level, the second clock signal terminal inputs a high level, and the third clock signal terminal inputs a high level, configured to provide the high level input from the input signal terminal to the first node, and provide a low level of the second voltage terminal to the second node, so that the first output terminal and the second output terminal both output high levels.

14. A scan driving circuit, comprising: shift registers, arranged in a cascaded manner, wherein each of the shift registers includes: an input module, electrically connected to a signal input terminal and a first clock signal terminal, and configured to provide a signal of the signal input terminal to a first node in response to a signal of the first clock signal terminal; a control module, electrically connected to a first voltage terminal, a second clock signal terminal, and a second node, and configured to provide a voltage of the first voltage terminal to the first node in response to a voltage of the second node and a signal of the second clock signal terminal; a reset module, electrically connected to a second voltage terminal and the first clock signal terminal, and configured to provide a voltage of the second voltage terminal to the second node in response to the signal of the first clock signal terminal; a first output module, electrically connected to the first node and the second clock signal terminal, and configured to provide the signal of the second clock signal terminal to a first output terminal in response to the voltage of the first node; a second output module, electrically connected to the first node and a third clock signal terminal, and configured to provide a signal of the third clock signal terminal to a second output terminal in response to the voltage of the first node; and a stabilization module, electrically connected to the second node and the first voltage terminal, and configured to provide the voltage of the first voltage terminal to the first output terminal and the second output terminal respectively in response to the voltage of the second node, wherein: a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module, and the stabilization module includes: a first transistor, wherein a first terminal of the first transistor is electrically connected to the first voltage terminal, a second terminal of the first transistor is electrically connected to the first output terminal, and a control terminal of the first transistor is electrically connected to the second node; a second transistor, wherein a first terminal of the second transistor is electrically connected to the first voltage terminal, a second terminal of the second transistor is electrically connected to the second output terminal, and a control terminal of the second transistor is electrically connected to the second node; and a first capacitor, wherein a first plate of the first capacitor is electrically connected to the first voltage terminal, and a second plate of the first capacitor is electrically connected to the second node, the first output module includes: a third transistor, wherein a first terminal of the third transistor is electrically connected to the first output terminal, and a second terminal of the third transistor is electrically connected to the second clock signal terminal; and a second capacitor, wherein a first plate of the second capacitor is electrically connected to the first output terminal, and a second plate of the second capacitor is electrically connected to a control terminal of the third transistor; and the second output module includes: a fourth transistor, wherein a first terminal of the fourth transistor is electrically connected to the second output terminal, and a second terminal of the fourth transistor is electrically connected to the third clock signal terminal; and a third capacitor, wherein a first plate of the third capacitor is electrically connected to the second output terminal, and a second plate of the third capacitor is electrically connected to a control terminal of the fourth transistor, and a capacitance of the third capacitor is greater than a capacitance of the second capacitor; an initial signal line; a first clock signal line; a second clock signal line; and a third clock signal line, wherein: the signal input terminal of a first-stage shift register is electrically connected to the initial signal line; except for the first-stage shift register, the signal input terminal of each stage shift register is electrically connected to one of the second output terminal and the first output terminal of a previous stage shift register; for a 3n-th stage shift register, a first clock signal terminal thereof is electrically connected to the first clock signal line, a second clock signal terminal thereof is electrically connected to the second clock signal line, and a third clock signal terminal thereof is electrically connected to the third clock signal line; for a 3n+1st stage shift register, a first clock signal terminal thereof is electrically connected to the third clock signal line, a second clock signal terminal thereof is electrically connected to the first clock signal line, and a third clock signal terminal thereof is electrically connected to the second clock signal line; for a 3n+2nd stage shift register, a first clock signal terminal thereof is electrically connected to the second clock signal line, a second clock signal terminal thereof is electrically connected to the third clock signal line, and a third clock signal terminal thereof is electrically connected to the first clock signal line; and pulses of the first clock signal line, the second clock signal line, and the third clock signal line do not overlap with each other, and are arranged sequentially in time, wherein: n is 0 or a positive integer.

15. A display panel, comprising: a scan driving circuit, wherein the scan driving circuit includes: shift registers, arranged in a cascaded manner, wherein each of the shift registers includes: an input module, electrically connected to a signal input terminal and a first clock signal terminal, and configured to provide a signal of the signal input terminal to a first node in response to a signal of the first clock signal terminal; a control module, electrically connected to a first voltage terminal, a second clock signal terminal, and a second node, and configured to provide a voltage of the first voltage terminal to the first node in response to a voltage of the second node and a signal of the second clock signal terminal; a reset module, electrically connected to a second voltage terminal and the first clock signal terminal, and configured to provide a voltage of the second voltage terminal to the second node in response to the signal of the first clock signal terminal; a first output module, electrically connected to the first node and the second clock signal terminal, and configured to provide the signal of the second clock signal terminal to a first output terminal in response to the voltage of the first node; a second output module, electrically connected to the first node and a third clock signal terminal, and configured to provide a signal of the third clock signal terminal to a second output terminal in response to the voltage of the first node; and a stabilization module, electrically connected to the second node and the first voltage terminal, and configured to provide the voltage of the first voltage terminal to the first output terminal and the second output terminal respectively in response to the voltage of the second node, wherein: a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module, and the stabilization module includes: a first transistor, wherein a first terminal of the first transistor is electrically connected to the first voltage terminal, a second terminal of the first transistor is electrically connected to the first output terminal, and a control terminal of the first transistor is electrically connected to the second node; a second transistor, wherein a first terminal of the second transistor is electrically connected to the first voltage terminal, a second terminal of the second transistor is electrically connected to the second output terminal, and a control terminal of the second transistor is electrically connected to the second node; and a first capacitor, wherein a first plate of the first capacitor is electrically connected to the first voltage terminal, and a second plate of the first capacitor is electrically connected to the second node, the first output module includes: a third transistor, wherein a first terminal of the third transistor is electrically connected to the first output terminal, and a second terminal of the third transistor is electrically connected to the second clock signal terminal; and a second capacitor, wherein a first plate of the second capacitor is electrically connected to the first output terminal, and a second plate of the second capacitor is electrically connected to a control terminal of the third transistor; and the second output module includes: a fourth transistor, wherein a first terminal of the fourth transistor is electrically connected to the second output terminal, and a second terminal of the fourth transistor is electrically connected to the third clock signal terminal; and a third capacitor, wherein a first plate of the third capacitor is electrically connected to the second output terminal, and a second plate of the third capacitor is electrically connected to a control terminal of the fourth transistor, and a capacitance of the third capacitor is greater than a capacitance of the second capacitor; an initial signal line; a first clock signal line; a second clock signal line; and a third clock signal line, wherein: the signal input terminal of a first-stage shift register is electrically connected to the initial signal line; except for the first-stage shift register, the signal input terminal of each stage shift register is electrically connected to one of the second output terminal and the first output terminal of a previous stage shift register; for a 3n-th stage shift register, a first clock signal terminal thereof is electrically connected to the first clock signal line, a second clock signal terminal thereof is electrically connected to the second clock signal line, and a third clock signal terminal thereof is electrically connected to the third clock signal line; for a 3n+1st stage shift register, a first clock signal terminal thereof is electrically connected to the third clock signal line, a second clock signal terminal thereof is electrically connected to the first clock signal line, and a third clock signal terminal thereof is electrically connected to the second clock signal line; for a 3n+2nd stage shift register, a first clock signal terminal thereof is electrically connected to the second clock signal line, a second clock signal terminal thereof is electrically connected to the third clock signal line, and a third clock signal terminal thereof is electrically connected to the first clock signal line; and pulses of the first clock signal line, the second clock signal line, and the third clock signal line do not overlap with each other, and are arranged sequentially in time, wherein: n is 0 or a positive integer; a plurality of scan signal lines; and a plurality of pixel driving circuits, wherein: the first output terminal and the second output terminal of the shift registers of the scan driving circuit are electrically connected to the plurality of scan signal lines; and the plurality of scan signal lines is electrically connected to the plurality of pixel driving circuits.

16. A display device, comprising: the display panel according to claim 15 .