Position-Based Rendering Apparatus and Method for Multi-Die/GPU Graphics Processing

2. The method of claim 1, wherein the vertex visibility data generated at each graphics processor comprises an indication of whether each primitive associated with the graphics draws assigned the graphics processor is visible within each of the plurality of tiles.

3. The method of claim 1, wherein the vertex visibility data generated at each graphics processor comprises an indication of whether each primitive associated with the graphics draws assigned to the graphics processor is visible within any of the tiles assigned to the processor but not of a specific tile.

4. The method of claim 1, wherein the vertex visibility data is generated via position-only shading for all tiles per vertex simultaneously.

5. The method of claim 1, wherein the plurality of graphics draws is distributed to the plurality of graphics processors based on a vertex count-based scheduling scheme.

6. The method of claim 1, wherein the plurality of graphics draws is distributed to the plurality of graphics processors based on a graphics processor idleness-based scheduling scheme.

7. The method of claim 1, wherein the plurality of graphics draws is distributed to the plurality of graphics processors based on a round robin scheduling scheme.

8. The method of claim 1, wherein the vertex visibility data generated at each graphics processor is distributed to all other graphics processors.

9. The method of claim 1, wherein the vertex visibility data generated at each graphics processor is distributed to a subset of the other graphics processors.

10. The method of claim 1, wherein the vertex visibility data generated at each graphics processor is distributed to other graphics processors via point-to-point inter-die interconnects.

12. The method of claim 11, wherein limiting geometry work processing comprises performing geometry work using only those primitives which are visible.

15. The graphics processing system of claim 14, wherein the vertex visibility data generated at each graphics processor comprises an indication of whether each primitive associated with the graphics draws assigned the graphics processor is visible within each of the plurality of tiles.

16. The graphics processing system of claim 14, wherein the vertex visibility data generated at each graphics processor comprises an indication of whether each primitive associated with the graphics draws assigned to the graphics processor is visible within any of the tiles assigned to the processor but not of a specific tile.

17. The graphics processing system of claim 14, wherein the vertex visibility data is generated via position-only shading for all tiles per vertex simultaneously.

18. The graphics processing system of claim 14, wherein the plurality of graphics draws is distributed to the plurality of graphics processors based on a vertex count-based scheduling scheme, a graphics processor idleness-based scheduling scheme, or a round robin scheduling scheme.

19. The graphics processing system of claim 14, wherein the vertex visibility data generated at each graphics processor is distributed to all other graphics processors.

20. The graphics processing system of claim 14, wherein the vertex visibility data generated at each graphics processor is distributed to a subset of the other graphics processors.

21. The graphics processing system of claim 14, wherein the vertex visibility data generated at each graphics processor is distributed to other graphics processors via point-to-point inter-die interconnects.

22. The graphics processing system of claim 14, wherein each of the plurality of graphics processors is further to compare primitives included in the vertex data for each tile to identify one or more primitives which are visible within each tile's region and to identify occluded primitives in the vertex data.

23. The graphics processing system of claim 22, wherein the geometry shader is to limit geometry work to be performed by performing geometry work using only those primitives which are visible.

24. The graphics processing system of claim 23, wherein each of the plurality of graphics processors is further to rasterize the subset of tiles assigned to the graphics processor to generate pixels for each of the tiles in the assigned subset.