Communication Systems with Serial Peripheral Interface Functionality

1. An apparatus with serial peripheral interface (SPI) functionality, comprising: a first node transceiver, wherein the first node transceiver includes transceiver circuitry to receive a signal transmitted over two wires of a two-wire bus from a second node transceiver; wherein the first node transceiver includes Inter-Integrated Circuit (I2C) circuitry to allow the first node transceiver to interface with an I2C slave, the second node transceiver includes SPI circuitry to allow the second node transceiver to interface with an SPI host, and the I2C slave is to respond to commands transmitted from the SPI host and over the two-wire bus.

3. The apparatus of claim 2, wherein the first SPI command includes an I2C read request command, the first I2C command includes an I2C read command, and the second I2C command includes an I2C read command.

4. The apparatus of claim 3, wherein the SPI circuitry is to receive, from the first node transceiver via the transceiver circuitry, read data in response to the read command transmitted to the first node transceiver.

5. The apparatus of claim 4, wherein the read data is provided to the I2C circuitry of the first node transceiver by the I2C slave.

6. The apparatus of claim 4, wherein the SPI circuitry is to receive, from the SPI host, a first-in-first-out (FIFO) read command, and in response to receipt of the FIFO read command, provide the read data to the SPI host.

7. The apparatus of claim 2, wherein the first SPI command includes an I2C write command, the first I2C command includes a write command, and the second I2C command includes a write command.

8. The apparatus of claim 2, wherein the first SPI command includes an indicator of the first node transceiver and an indicator of the I2C slave.

9. The apparatus of claim 1, wherein the SPI circuitry includes a slave select port, a bit clock port, a master-out-slave-in port, and a master-in-slave-out port, wherein the I2C circuitry includes a data port and a clock port.

10. The apparatus of claim 1, wherein the transceiver circuitry is first transceiver circuitry, the two wires are a first two wires, the first node transceiver further includes second transceiver circuitry to receive a signal transmitted over a second two wires of the two-wire bus from a third node transceiver, and (a) the first transceiver circuitry is upstream transceiver circuitry and the second transceiver circuitry is downstream transceiver circuitry, or (b) the first transceiver circuitry is downstream transceiver circuitry and the second transceiver circuitry is upstream transceiver circuitry.

12. The apparatus of claim 1, wherein the first node transceiver is a slave node transceiver.

13. The apparatus of claim 1, further comprising: the SPI host.

14. The apparatus of claim 1, further comprising: the second node transceiver.

15. The apparatus of claim 1, further comprising: the I2C slave.

16. The apparatus of claim 1, wherein the two-wire bus includes an unshielded twisted pair.

17. The apparatus of claim 1, wherein the apparatus is at least partially included in a vehicle.