Method and Apparatus for Protecting a Puf Generator

2. The PUF generator of claim 1, wherein the initialization data of the plurality of bit cells are predetermined based on their initial logical states before the PUF cell array stores any user data and the initial logical states of the plurality of bit cells are equal to all logic 0s or all logic 1 s.

3. The PUF generator of claim 1, wherein the voltage tempering event happens when there is a voltage droop or glitch of the supply voltage of the PUF cell array.

5. The PUF generator of claim 4, wherein the reset circuit is configured to set the plurality of bit cells to their initial logical states simultaneously.

6. The PUF generator of claim 4, wherein the reset circuit comprises a finite state machine (FSM) that resets bit cells of each row to their initial logical states, one row at a time.

12. The PUF generator of claim 1, wherein the PUF cell array is a memory cell array configured for storing user data.

14. The memory device of claim 13, wherein the initialization data of the plurality of bit cells are predetermined based on their initial logical states before the memory cell array stores any user data and the initial logical states of the plurality of bit cells are equal to all logic 0s or all logic 1s.

20. The method of claim 18, wherein bit cells of each row of the memory cell array are set to their initial logical states, one row at a time.