Multiple Busses Within a Systolic Array Processing Element

3. The processing element of claim 2, wherein a passive interconnect of the one or more passive interconnects of the processing element corresponds to the active interconnect of the second plurality of interconnects of the subsequent processing element.

5. The processing element of claim 1, wherein a set of inputs are provided to the set of input ports, the set of inputs comprising a weight and an input data element.

7. The processing element of claim 6, wherein the multiplier is further configured to receive a weight from the first input port.

8. The processing element of claim 7, wherein the multiplication operation is further based on an input from a third input port, wherein the multiplier is further configured to receive an input data element from the third input port.

12. The processing element of claim 6, wherein the one or more passive interconnects are electronically isolated from the multiplier of the processing element.

13. The processing element of claim 6, wherein each interconnect of the plurality of interconnects are for one or more row-oriented busses.

14. The processing element of claim 6, wherein a passive interconnect of the one or more passive interconnects of the processing element corresponds to an active interconnect of a second plurality of interconnects of the subsequent processing element.

15. The processing element of claim 6, wherein the active interconnect of the processing element corresponds to a passive interconnect of a second plurality of interconnects of the subsequent processing element.

17. The processing element of claim 16, wherein the circuitry is further configured to receive a weight from the first input port of the set of input ports.

18. The processing element of claim 17, wherein the circuitry is further coupled to a second active interconnect of the plurality of interconnects, the second active interconnect configured to obtain an input data element from a third input port of the set of input ports, the circuitry further configured to receive the input data element from a third input port of the set of input ports.

21. The processing element of claim 16, wherein the mathematical operation comprises multiplying two or more inputs.

22. The processing element of claim 16, wherein each of the one or more passive interconnects is electronically isolated from the circuitry of the processing element.

23. The processing element of claim 16, wherein the set of output ports is configured to be coupled to a second set of input ports of the subsequent processing element, such that individual output ports of the set of output ports are coupled to individual input ports of the second set of input ports.