Machine Learning Accelerator

2. The neural network circuit according to claim 1, wherein the transistors of the at least two arrays connect to a single bitline for receiving the positive current weighted component and the negative weighted current component combined with reference signals.

3. The neural network circuit according to claim 1, wherein a comparator compares the combined positive current component and negative current component combined with reference signals to a pre-determined reference value.

4. The neural network circuit according to claim 1, wherein first transistors of one of a first array connect to a first bitline, different from a second bitline, to which second transistors of a second arrays connect, the first bitline and second bitline, respectively, configured to receive a combined positive current component and associated reference signal, or the combined negative weighted current component and associated reference signal.

5. The neural network circuit according to claim 4, further comprising a differential amplifier configured to amplify a difference between the combined positive weighted current component and negative reference signal with the combined negative weighted current component and positive reference signal.

6. The neural network circuit according to claim 1, wherein the transistors of one of the arrays are laid out in a single physical plane of an electronic component.

7. The neural network circuit according to claim 6, wherein a plurality of planes of transistors are stacked vertically.

8. The neural network circuit according to claim 1, wherein the positive weighted current component and negative weighted current component are provided by driving multiple transistors in parallel.

9. The neural network circuit according to claim 1, wherein the transistors generating the positive weighted current component or negative weighted current component are laid out on a horizontal plane of a three-dimensional array.

10. The neural network circuit according to claim 1, wherein the transistors are operated in subthreshold region and act as current sources controlled by an input gate voltage.

11. The neural network circuit according to claim 1, wherein the reference network is implemented as one or more transistors in parallel.

12. The neural network circuit according to any of claim 1, wherein the reference network is implemented as one or more programmable resistive memories in parallel.