Methods and Systems of Implementing Positive and Negative Neurons in a Neural Array-Based Flash Memory

2. The neural network compute circuit of claim 1, wherein the affine function f( ) is the identity function.

4. The neural circuit of claim 3, wherein the affine function f( ) is the identity function.

8. The neural circuit of claim 7, wherein XNMAX is a maximum negative input value expected for the neural circuit; XNMAX=maximum(|Xi|) for all i where Xi<0 for all expected values of Xi.

9. The neural circuit of claim 8, wherein the expected values of Xi are estimated using a dataset.

10. The neural circuit of claim 7, wherein XNMAX is set to a fixed vale, e.g. zero.

11. The neural circuit of claim 7, wherein YNMAX comprises a largest negative weight in the neuron circuit; YNMAX=maximum(|Yi|) for all i where Yi<0.

12. The neural circuit of claim 11, wherein YNMAX is set to a fixed vale, e.g. zero.

13. The neural network compute circuit of claim 7, wherein the Σ(Xi′*Yi′) is in one neuron for each output in the plurality of neurons and one Σ(Xi′*YNMAX) adjustment neuron is added to the plurality of neurons.

14. The neural network compute circuit of claim 13, wherein the output from the Σ(Xi′*YNMAX) adjustment neuron is subtracted from each of the Σ(Xi′*Yi′) neurons.

15. The neural network compute circuit of claim 13, wherein the output from the Σ(Xi′*YNMAX) adjustment neurons and the output of the Σ(Xi′*Yi′) neuron are converted to digital through ADCs.

16. The neural network compute circuit of claim 15, wherein the ADC output from the Σ(Xi′*YNMAX) adjustment neuron is subtracted from the ADC output of the Σ(Xi′*Yi′) neurons.

17. The neural circuit of claim 13, wherein the adjustment neuron provides a mirror adjustment current.

18. The neural circuit of claim 7, wherein each synapse output of the plurality of neural cells is coupled with a current input source of the plurality of current input sources.

19. The neural circuit of claim 18, wherein the outputs to be subtracted are currents taken through a set of current mirrors.

20. The neural circuit of claim 19, wherein the neuron receives two currents and utilizes a mirror adjustment current.

21. The method of claim 20, wherein each input value is split into a positive voltage and a negative voltage.

22. The neural circuit of claim 7, wherein the plurality of non-volatile memory cells are MLC flash cells.

23. The neural circuit of claim 7, wherein the plurality of non-volatile memory cells are SLC flash cells are ordered from a most significant bit (MSB) level to a least significant bit (LSB) level.