Legal claims defining the scope of protection, as filed with the USPTO.
2. The cache memory of claim 1, wherein the one or more peripheral circuits are configured to identify which bits of the CPU address form the index portion based on the way quantity indication.
3. The cache memory of claim 2, wherein, responsive to M being greater than one and determining that the particular CPU instruction is stored in the cache memory based on the identified tag portion and tag data stored in the cache memory, the one or more peripheral circuits are configured to read the cache memory to retrieve the particular CPU instruction using the index portion as cache memory address data.
4. The cache memory of claim 2, wherein, in response to the way quantity indication indicating that the instruction memory portion and the tag memory portion are to be subdivided into a plurality of ways, the one or more peripheral circuits are configured to read the cache memory to retrieve the particular CPU instruction using the index portion and a portion of the tag portion as cache memory address data.
5. The cache memory of claim 2, wherein, in response to the way quantity indication indicating that the instruction memory portion and the tag memory portion are to be subdivided into a single way, the one or more peripheral circuits are configured to read the cache memory to retrieve the particular CPU instruction using the index portion as cache memory address data without using the tag portion as cache memory address data.
6. The cache memory of claim 1, wherein the one or more peripheral circuits comprise a peripheral comparison circuit configured to determine whether the particular CPU instruction is stored in the cache memory.
7. The cache memory of claim 1, wherein the one or more peripheral circuits comprise a peripheral comparison circuit configured to, in response to the way quantity indication indicating that the instruction memory portion and the tag memory portion are to be subdivided into a plurality of ways, identify which of the plurality of ways of the instruction memory portion the particular CPU instruction is stored in.
9. The method of claim 8, further comprising, with the one or more peripheral circuits, identifying which bits of the CPU address form the index portion based on the way quantity indication.
10. The method of claim 9, further comprising, with the one or more peripheral circuits, responsive to M being greater than one and determining that the particular CPU instruction is stored in the cache memory based on the identified tag portion and tag data stored in the cache memory, reading the cache memory to retrieve the particular CPU instruction using the index portion as cache memory address data.
11. The method of claim 9, further comprising, in response to the way quantity indication indicating that the instruction memory portion and the tag memory portion are to be subdivided into a plurality of ways, with the one or more peripheral circuits, reading the cache memory to retrieve the particular CPU instruction using the index portion and a portion of the tag portion as cache memory address data.
12. The method of claim 9, further comprising, in response to the way quantity indication indicating that the instruction memory portion and the tag memory portion are to be subdivided into a single way, with the one or more peripheral circuits, reading the cache memory to retrieve the particular CPU instruction using the index portion as cache memory address data without using the tag portion as cache memory address data.
13. The method of claim 8, wherein the one or more peripheral circuits comprise a peripheral comparison circuit, and the method further comprises, with the peripheral comparison circuit, determining whether the particular CPU instruction is stored in the cache memory.
14. The method of claim 8, wherein the one or more peripheral circuits comprise a peripheral comparison circuit, and the method further comprises, with the peripheral comparison circuit, in response to the way quantity indication indicating that the instruction memory portion and the tag memory portion are to be subdivided into a plurality of ways, identifying which of the plurality of ways of the instruction memory portion the particular CPU instruction is stored in.
Unknown
October 11, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.