Signal Power Management Circuits and Smart Cards Including the Same

2. The signal power management circuit of claim 1, wherein the first voltage level is a voltage level of a direct current (DC) component of the first rectified voltage, wherein the second voltage level is a voltage level of a DC component of the second rectified voltage, and wherein the signal detector is configured to detect the signal component of the received radio frequency signal by generating a current determined by a difference between the voltage level of the DC component of the first rectified voltage and the voltage level of a DC component of the second rectified voltage.

3. The signal power management circuit of claim 1, wherein the second voltage level is lower than the first voltage level.

5. The signal power management circuit of claim 4, wherein the first regulator is configured to block noise generated due to operation of the switched capacitor converter.

9. The signal power management circuit of claim 8, wherein the first current mirror circuit includes a fifth transistor and a sixth transistor, and wherein types of the first to fourth transistors are different from types of the fifth and sixth transistors.

10. The signal power management circuit of claim 6, wherein a threshold voltage of the first transistor equals a threshold voltage of the second transistor, and wherein the signal detector generates the current determined by the difference between the first voltage level of the first rectified voltage and the second voltage level of the second rectified voltage using the first and second transistors.

12. The signal power management circuit of claim 11, wherein a threshold voltage of the first transistor equals a threshold voltage of the second transistor.

13. The signal power management circuit of claim 11, wherein the second rectified voltage is lower than the first rectified voltage.

15. The signal power management circuit of claim 14, wherein the first, second, fifth, and sixth transistors include p-channel metal-oxide-semiconductor (PMOS) transistors, and wherein the third and fourth transistors include n-channel metal-oxide-semiconductor (NMOS) transistors.

17. The smart card of claim 16, further comprising a biometric authentication sensor coupled to the signal power management circuit and configured to receive the internal power and detect biometric information of a user.

20. The smart card of claim 19, wherein a threshold voltage of the first transistor equals a threshold voltage of the second transistor.