Legal claims defining the scope of protection, as filed with the USPTO.
2. The system of claim 1 wherein the internal SYSREF signal (sysref_posedge_div1) is synchronous with the second system reference signal (SYSREF_2).
3. The system of claim 1 wherein the first clock signal (CLK_1) and first system reference signal (SYSREF_1) are responsive to external clock and SYSREF signals that satisfy the requirements of a JESD204B/204C specification.
8. The system of claim 7 wherein the sixth reference signal (SYSREF_PULSE_divn) is synchronous with the second reference signal (SYSREF_2).
11. The system of claim 1 wherein the first circuit is an analog circuit.
13. The method of claim 12 wherein the internal SYSREF signal (sysref_posedge_div1) is synchronous with the second system reference signal (SYSREF_2).
14. The method of claim 12 wherein the first clock signal (CLK_1) and first system reference signal (SYSREF_1) are responsive to external clock and SYSREF signals that satisfy the requirements of a JESD204B/204C specification.
19. The method of claim 18 wherein the sixth reference signal (SYSREF_PULSE_divn) is synchronous with the second reference signal (SYSREF_2).
21. The method of claim 12 wherein the first circuit is an analog circuit.
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October 25, 2022
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