Compact NUMA-aware Locks

2. The method of claim 1, wherein the identified waiting thread executes on one of a plurality of processors of a computing system also executing the first controlling thread, and wherein the one or more other waiting threads execute on another one of the plurality of processors with different memory access characteristics than the processor executing the first controlling thread.

3. The method of claim 1, wherein the respective wait structures of the one or more other waiting threads are linked together to form the secondary queue.

4. The method of claim 1, wherein the one or more other waiting threads are moved to the secondary queue preserving the order in which they were enqueued in the FIFO queue.

6. The method of claim 5, wherein the first controlling thread and the second controlling thread execute on one of a plurality of processors of a computing system, wherein the one or more other waiting threads execute on another one of the plurality of processors with different memory access characteristics than the processor executing the first controlling thread and the second controlling thread, and wherein the moving the one or more other waiting threads from the secondary queue to the FIFO queue is performed responsive to determining that no thread of the plurality of waiting threads executes on the one of a plurality of processors executing the second controlling thread.

7. The method of claim 4, the moving of the one or more other waiting threads from the secondary queue to the FIFO queue comprising inserting the one or more other waiting threads at the head of the FIFO queue to ensure fairness, wherein the respective wait structures of the one or more other waiting threads are linked together preserving the order in which they were enqueued in the FIFO queue.

9. The one or more non-transitory computer-accessible storage media of claim 8, wherein the identified waiting thread executes on one of a plurality of processors of a computing system also executing the first controlling thread, and wherein the one or more other waiting threads execute on another one of the plurality of processors with different memory access characteristics than the processor executing the first controlling thread.

10. The one or more non-transitory computer-accessible storage media of claim 8, wherein the respective wait structures of the one or more other waiting threads are linked together to form the secondary queue.

11. The one or more non-transitory computer-accessible storage media of claim 8, wherein the one or more other waiting threads are moved to the secondary queue preserving the order in which they were enqueued in the FIFO queue.

13. The one or more non-transitory computer-accessible storage media of claim 12, wherein the first controlling thread and the second controlling thread execute on one of a plurality of processors of a computing system, wherein the one or more other waiting threads execute on another one of the plurality of processors with different memory access characteristics than the processor executing the first controlling thread and the second controlling thread, and wherein the moving the one or more other waiting threads from the secondary queue to the FIFO queue is performed responsive to determining that no thread of the plurality of waiting threads executes on the one of a plurality of processors executing the second controlling thread.

14. The one or more non-transitory computer-accessible storage media of claim 12, the moving of the one or more other waiting threads from the secondary queue to the FIFO queue comprising inserting the one or more other waiting threads at the head of the FIFO queue to ensure fairness, wherein the respective wait structures of the one or more other waiting threads are linked together preserving the order in which they were enqueued in the FIFO queue.

16. The system of claim 15, wherein the one or more processors is a plurality of processors, wherein the identified waiting thread executes on one of the plurality of processors also executing the first controlling thread, and wherein the one or more other waiting threads execute on another one of the plurality of processors with different memory access characteristics than the processor executing the first controlling thread.

17. The system of claim 15, wherein the operation to transfer control of the lock is further configured to move the one or more other waiting threads to the secondary queue preserving the order in which they were enqueued in the FIFO queue.

19. The system of claim 18, wherein the one or more processors is a plurality of processors, wherein the first controlling thread and the second controlling thread execute on one of a plurality of processors of a computing system, wherein the one or more other waiting threads execute on another one of the plurality of processors with different memory access characteristics than the processor executing the first controlling thread and the second controlling thread, and wherein moving the one or more other waiting threads from the secondary queue to the FIFO queue is performed responsive to a determination that no thread of the plurality of waiting threads executes on the one of a plurality of processors executing the second controlling thread.

20. The system of claim 18, wherein the operation to transfer control of the lock is configured to link the respective wait structures of the one or more other waiting threads together preserving the order in which they were enqueued in the FIFO queue, and wherein to move the one or more other threads from the secondary queue to the FIFO queue, the operation to transfer control of the lock is configured to insert the one or more other threads at the head of the FIFO queue to ensure fairness.