11513939

Multi-Core I/O Trace Analysis

PublishedNovember 29, 2022
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
9 claims

Legal claims defining the scope of protection, as filed with the USPTO.

3

3. The method of claim 2, wherein, for each of the at least first computing module, each of the plurality of entries in the second data structure includes a pointer to a memory address of the corresponding entry in the at least first data structure, and includes less information than an amount of information recorded in the corresponding entry.

5

5. The method of claim 2, wherein the first information is stored in a third data structure in the local memory of the first computing module, the third data structure derived at least in part from a respective second data structure of the at least second computing module, and the third data structure including a plurality of entries, each entry corresponding to a respective entry of the respective second data structure and including the specified time and the pointer to the memory address included in the respective entry.

6

6. The method of claim 5, wherein the pair of recorded entries of the first information are included in the third data structure.

12

12. The storage system of claim 11, wherein, for each of the at least first computing module, each of the plurality of entries in the second data structure includes a pointer to a memory address of the corresponding entry in the at least first data structure, and includes less information than an amount of information recorded in the corresponding entry.

14

14. The storage system of claim 11, wherein the first information is stored in a third data structure in the local memory of the first computing module, the third data structure derived at least in part from a respective second data structure of the at least second computing module, and the third data structure including a plurality of entries, each entry corresponding to a respective entry of the respective second data structure and including the specified time and the pointer to the memory address included in the respective entry.

15

15. The storage system of claim 14, wherein the pair of recorded entries of the first information are included in the third data structure.

19

19. The one or more non-transitory computer-readable media of claim 18, wherein, for each of the at least first computing module, each of the plurality of entries in the second data structure includes a pointer to a memory address of the corresponding entry in the at least first data structure, and includes less information than an amount of information recorded in the corresponding entry.

21

21. The one or more non-transitory computer-readable media of claim 18, wherein the first information is stored in a third data structure in the local memory of the first computing module, the third data structure derived at least in part from a respective second data structure of the at least second computing module, and the third data structure including a plurality of entries, each entry corresponding to a respective entry of the respective second data structure and including the specified time and the pointer to the memory address included in the respective entry.

22

22. The one or more non-transitory computer-readable media of claim 21, wherein the pair of recorded entries of the first information are included in the third data structure.

Patent Metadata

Filing Date

Unknown

Publication Date

November 29, 2022

Inventors

Gabriel Hershkovitz
Jerome J. Cartmell
Arieh Don

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Cite as: Patentable. “MULTI-CORE I/O TRACE ANALYSIS” (11513939). https://patentable.app/patents/11513939

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