Deadlock Condition Avoidance in a Data Processing System with a Shared Slave

5. The processing system of claim 1 wherein the deadlock condition detection control circuit provides the deadlock condition indicator to the arbitration circuitry, and when the deadlock condition indicator is asserted, the arbitration circuitry discontinues allowing the first bus master devices to occupy the port associated with the bus slave device.

6. The processing system of claim 1, wherein when the deadlock condition indicator is asserted, an interrupt is generated which can be detected and handled by an interrupt handler system.

8. The processing system of claim 7 wherein the arbitration circuitry is further configured to relinquish access to the one of the bus slave devices to the second of the bus master devices when the deadlock condition indicator is asserted.

9. The processing system of claim 7 wherein the arbitration circuitry further configured to relinquish access to the one of the bus slave devices to one of the bus master devices with a next highest priority when the deadlock condition indicator is asserted.

13. The processing system of claim 7, wherein when the deadlock condition indicator is asserted, an interrupt is generated which can be detected and handled by an interrupt handler system.