11553446

Technologies for Managing Internal Time Synchronization

PublishedJanuary 10, 2023
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
17 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The apparatus of claim 1, wherein the processor circuitry is to determine the transport delay value by determining an average of the transmit path delay and the receive path delay.

3

3. The apparatus of claim 1, wherein the first device is an I/O device of an internet-of-things (IoT) device and the second device is a central timer of the IoT device.

4

4. The apparatus of claim 1, wherein the processor circuitry is to retrieve the first time, the second time, the third time, and the fourth time from corresponding registers of the first device.

5

5. The apparatus of claim 1, wherein the processor circuitry is to update the timestamp value by subtracting the transport delay value from the timestamp value.

6

6. The apparatus of claim 1, wherein the processor circuitry is to update the timestamp value during a boot time of the first device.

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7. The apparatus of claim 1, wherein the processor circuitry is to retrieve the second time and the third time from one or more data fields of the second message.

9

9. The non-transitory computer readable medium of claim 8, wherein the instructions, when executed, cause the processor circuitry to determine the transport delay value by determining an average of the transmit path delay and the receive path delay.

10

10. The non-transitory computer readable medium of claim 8, wherein the first device is an I/O device of an internet-of-things (IoT) device and the second device is a central timer of the IoT device.

11

11. The non-transitory computer readable medium of claim 8, wherein the instructions, when executed, cause the processor circuitry to retrieve the first time, the second time, the third time, and the fourth time from corresponding registers of the first device.

12

12. The non-transitory computer readable medium of claim 8, wherein the instructions, when executed, cause the processor circuitry to update the timestamp value by subtracting the transport delay value from the timestamp value.

13

13. The non-transitory computer readable medium of claim 8, wherein the instructions, when executed, cause the processor circuitry to update the timestamp value during a boot time of the first device.

14

14. The non-transitory computer readable medium of claim 8, wherein the instructions, when executed, cause the processor circuitry to retrieve the second time and the third time from one or more data fields of the second message.

16

16. The method of claim 15, further including determining, by executing an instruction with the processor circuitry, the transport delay value by determining an average of the transmit path delay and the receive path delay.

17

17. The method of claim 15, wherein the first device is an I/O device of an internet-of-things (IoT) device and the second device is a central timer of the IoT device.

18

18. The method of claim 15, further including retrieving, by executing an instruction with the processor circuitry, the first time, the second time, the third time, and the fourth time from corresponding registers of the first device.

19

19. The method of claim 15, further including updating, by executing an instruction with the processor circuitry, the timestamp value by subtracting the transport delay value from the timestamp value.

20

20. The method of claim 15, further including updating, by executing an instruction with the processor circuitry, the timestamp value during a boot time of the first device.

Patent Metadata

Filing Date

Unknown

Publication Date

January 10, 2023

Inventors

Kishore Kasichainula

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Cite as: Patentable. “TECHNOLOGIES FOR MANAGING INTERNAL TIME SYNCHRONIZATION” (11553446). https://patentable.app/patents/11553446

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