Legal claims defining the scope of protection, as filed with the USPTO.
2. The HWA of claim 1, further comprising a constant false alarm rate (CFAR) engine in a CFAR detection path parallel to the streaming series data path including a log-magnitude pre-processing block and a CFAR detector configured to detect radar target returns against a background.
4. The HWA of claim 1, further comprising a substrate that provides at least a semiconductor surface, wherein the HWA is formed in the semiconductor surface.
5. The HWA of claim 2, wherein the CFAR detection path shares at least one of a shared memory and logic with the FFT engine.
6. The HWA of claim 1, wherein the pre-processing block is configured to perform interference mitigation.
7. The HWA of claim 1, wherein the pre-processing operation performed by the circuit of the pre-processing block includes finite impulse response (FIR) filtering.
8. The HWA of claim 1, wherein the pre-processing operation performed by the circuit of the pre-processing block includes multiplying the set of samples received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT).
10. The radar sub-system of claim 9, wherein the state machine is a parameter-set based state machine wherein the parameter-sets are programmable, the parameter-sets configured to cause the HWA to perform a certain set of the operations, and wherein a sequence of executing the parameter-sets is defined.
12. The radar sub-system of claim 9, further comprising a constant false alarm rate (CFAR) engine in a CFAR detection path parallel to the streaming series data path including a log-magnitude pre-processing block and CFAR detector configured to detect radar target returns against a background.
13. The radar sub-system of claim 9, wherein the ADC buffers and the output buffers are both split memories.
14. The radar sub-system of claim 9, further comprising a substrate that provides at least a semiconductor surface, wherein the HWA is formed in the semiconductor surface.
16. The radar sub-system of claim 9, wherein the pre-processing block is configured to perform interference mitigation.
17. The radar sub-system of claim 9, wherein the pre-processing operation performed by the circuit of the pre-processing block includes finite impulse response (FIR) filtering.
18. The radar sub-system of claim 9, wherein the pre-processing operation performed by the circuit of the pre-processing block includes multiplying the radar data sample streams by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT).
21. The method of claim 19, further comprising determining whether to perform a finite impulse response filtering operation on the set of pre-processed samples using a third circuit or to bypass the third circuit.
23. The method of claim 19 further comprising determining a magnitude of the set of Fourier transformed samples.
25. The method of claim 19, wherein the FFT is a range FFT.
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February 14, 2023
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