11586377

Memory System and Control Method

PublishedFebruary 21, 2023
Assigneenot available in USPTO data we have
InventorsKoichi NAGAI
Technical Abstract

Patent Claims
13 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The memory system according to claim 1, wherein the secure erase target data includes valid data.

3

3. The memory system according to claim 1, wherein the secure erase target data includes only invalid data.

4

4. The memory system according to claim 1, wherein the controller is further configured to execute, in response to the first command, an unmap operation invalidating the secure erase target data.

5

5. The memory system according to claim 4, wherein the controller is configured to execute the unmap operation before the copy operation.

7

7. The memory system according to claim 1, wherein the controller is further configured to execute, in response to the first command, the data erasing operation on a free block from among free blocks in the plurality of blocks storing no valid data before a start of the copy operation and not used as one of the copy destination blocks when the free block was storing invalid data included among the secure erase target data when the first command was received.

9

9. The memory system according to claim 1, wherein the first logical area identifier includes one or more logical addresses that identify one or more secure erase target sectors.

10

10. The memory system according to claim 1, wherein the first logical area identifier includes one or more keys that identify one or more secure erase target values.

12

12. The memory system according to claim 1, wherein the secure erase target data includes invalid data previously associated with the first logical area identifier.

13

13. The memory system according to claim 1, wherein the first command designates the first logical area identifier.

14

14. The memory system according to claim 1, wherein the first logical area identifier is designated by a command from the host other than the first command.

16

16. The memory system according to claim 15, wherein the data erasing operation on the one or more first blocks is directly after the completion of the copy operation.

17

17. The memory system according to claim 15, wherein the data erasing operation on the one or more first blocks is performed after the completion of the copy operation in response to a second command from the host requesting a secure erase of secure erase target data.

19

19. The control method according to claim 18, wherein the secure erase target data includes invalid data previously associated with the first logical area identifier.

Patent Metadata

Filing Date

Unknown

Publication Date

February 21, 2023

Inventors

Koichi NAGAI

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Cite as: Patentable. “MEMORY SYSTEM AND CONTROL METHOD” (11586377). https://patentable.app/patents/11586377

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