11586797

Through-Silicon Vias in Integrated Circuit Packaging

PublishedFebruary 21, 2023
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
16 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The device structure of claim 1, wherein the pseudo metal layer is in contact with the middle portion.

3

3. The device structure of claim 1, wherein a horizontal dimension of each of the plurality of vias is smaller than a horizontal dimension of the middle portion.

4

4. The device structure of claim 1, wherein a horizontal dimension of the pseudo metal layer is substantially equal to a horizontal dimension of the middle portion.

5

5. The device structure of claim 1, wherein the pseudo metal layer is connected to an interconnect through an other plurality of vias on the first end.

6

6. The device structure of claim 5, wherein a dimension of each of the plurality of vias is different from a dimension of each of the other plurality of vias.

7

7. The device structure of claim 6, wherein the plurality of vias and the other plurality of vias are arranged in a two dimensional array with arrangements being different from each other.

8

8. The device structure of claim 5, wherein the middle portion is connected to an other interconnect on the second end.

10

10. The device structure of claim 8, wherein the middle portion is connected to the other interconnect through the plurality of vias.

11

11. The device structure of claim 1, wherein the middle portion is connected to at least one interconnect through the plurality of vias on at least one of the first end and the second end.

12

12. The device structure of claim 11, wherein the plurality of vias and the at least one interconnect are on the first end.

13

13. The device structure of claim 12, wherein the pseudo metal layer is between the at least one interconnect and the plurality of vias.

15

15. The device structure of claim 14, wherein the extended TSV structure is in contact with the first and second metal interconnects.

16

16. The device structure of claim 14, wherein a first side of the via is in contact with the first or the second metal interconnect, and wherein the extended TSV structure further comprises a pseudo metal layer formed over a second side of the via.

17

17. The device structure of claim 16, wherein the extended TSV structure further comprises a middle portion, wherein the pseudo metal layer is between the middle portion and the via, and wherein a horizontal dimension of the pseudo metal layer is substantially equal to a horizontal dimension of the middle portion.

19

19. The device structure of claim 18, wherein the pseudo metal layer and the second interconnect have an identical metal type.

20

20. The device structure of claim 18, wherein the extended TSV structure further comprises an other pseudo metal layer in contact with the first interconnect, and wherein a horizontal dimension of the pseudo metal layer is substantially equal to an other horizontal dimension of the other pseudo metal layer.

Patent Metadata

Filing Date

Unknown

Publication Date

February 21, 2023

Inventors

Fong-yuan CHANG
Chin-Chou LIU
Chin-Her CHIEN
Cheng-Hung YEH
Po-Hsiang HUANG
Sen-Bor JAN
Yi-Kan CHENG
Hsiu-Chuan SHU

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Cite as: Patentable. “Through-Silicon Vias in Integrated Circuit Packaging” (11586797). https://patentable.app/patents/11586797

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