Neural Network Memory with an Array of Variable Resistance Memory Cells

2. The apparatus of claim 1, wherein the variable resistance memory cell is a self-selecting memory cell comprising a single chalcogenide material to operate as a selection component and a storage component.

3. The apparatus of claim 2, wherein the neural memory unit controller being configured to apply the sub-threshold voltage pulse and the additional sub-threshold voltage pulses comprises the neural memory unit controller being configured to determine the single chalcogenide material is in an amorphous condition associated with a reset state.

4. The apparatus of claim 2, wherein the neural memory unit controller being configured to apply the sub-threshold voltage pulse and the additional sub-threshold voltage pulses comprises the neural memory unit controller being configured to alter the single chalcogenide material toward a condition associated with a set state.

6. The apparatus of claim 1, wherein the neural memory unit controller is configured to apply one of the additional sub-threshold voltage pulses to the variable resistance memory cell in response to an iteration of a learning algorithm indicating that increased learning has occurred.

7. The apparatus of claim 6, wherein the neural memory unit controller is further configured not to apply one of the additional sub-threshold voltage pulses to the variable resistance memory cell in response to the iteration of the learning algorithm indicating that additional learning has not occurred.

8. The apparatus of claim 6, wherein the neural memory unit controller is configured to apply the one of the additional sub-threshold voltage pulses as a relatively longer pulse to the variable resistance memory cell in response to an iteration of a learning algorithm indicating that relatively strong increased learning has occurred.

9. The apparatus of claim 6, wherein the neural memory unit controller is configured to apply more than one of the additional sub-threshold voltage pulses to the variable resistance memory cell in response to an iteration of a learning algorithm indicating that relatively strong increased learning has occurred.

10. The apparatus of claim 1, wherein the neural memory unit controller being configured to apply additional sub-threshold voltage pulses to the variable resistance memory cell comprises the neural memory unit controller being configured to change the threshold voltage of the variable resistance memory cell within a range of analog voltage values.

12. The apparatus of claim 11, wherein the neural memory unit controller is further configured to apply a subsequent respective sub-threshold voltage pulse via each of the plurality of first signal lines to change the threshold voltage of the respective variable resistance memory cell coupled to each of the plurality of first signal lines and to the particular second signal line in an analog fashion to effectuate a subsequent synaptic weight change based in part on the total analog value of the array.

13. The apparatus of claim 11, wherein the neural memory unit controller being configured to apply the respective sub-threshold voltage pulse via each of the first plurality of signal lines comprises the neural memory unit controller being configured to input a vector of data from a learning algorithm.

14. The apparatus of claim 13, wherein the neural memory unit controller being configured to read the voltage or the current from each of the plurality of second signal lines comprises the neural memory unit controller being configured to perform matrix multiplication of vectors each comprised of the respective threshold voltage of each variable resistance memory cell in each of the plurality of second signal lines.

18. The method of claim 15, further comprising determining a total analog value of the array of variable resistance memory cells, wherein the total analog value represents an aggregation of a synaptic weight for each of the variable resistance memory cells of the array.

19. The method of claim 15, wherein applying the weak sub-threshold voltage pulse and wherein applying the strong sub-threshold voltage pulse comprises decreasing a resistance of a chalcogenide material of the variable resistance memory cell.

20. The method of claim 15, wherein the array of variable resistance memory cells comprise self-selecting memory cells, each comprising a single chalcogenide material to operate as a selection component and a storage component.

22. The method of claim 21, wherein the second quantity is greater than the first quantity.

23. The method of claim 21, further comprising applying subsequent sub-threshold voltage pulses to the variable resistance memory cell in response to subsequent learning events until a sub-threshold voltage pulse causes the variable resistance memory cell to reach the set state.

24. The method of claim 23, wherein the method includes changing the threshold voltage in a range of analog values between a voltage associated with a reset state and the voltage associated with the set state, each of the range of analog values corresponding to a synaptic weight.