Integrated Circuit Configured to Carry Out Symmetric Encryption Operations Without Secret Key Transmission

3. The integrated circuit according to claim 2, wherein an output of the key registry delivers the recorded secret key to the decryption device to decrypt said encrypted binary data.

4. The integrated circuit according to claim 1, wherein the unique key is a unique hardware key recorded in the secure hardware environment.

5. The integrated circuit according to claim 1, wherein the decryption device is configured to carry out an AES decryption algorithm.

6. The integrated circuit according to claim 1, wherein the key generation device is configured to carry out an AES algorithm according to a counter mode with CBC-MAC in order to generate the secret key from the key number and the unique key.

7. The integrated circuit according to claim 1, wherein the key generation device is configured to implement an AES algorithm according to a mode GCM in order to generate the secret key from the key number and the unique key.

10. The integrated circuit according to claim 9, wherein the further signature generation device of the encryption system is identical to the signature generation device of the decryption system.

11. The integrated circuit according to claim 9, wherein the further signature generation device of the encryption system is same as the signature generation device of the decryption system.

12. The integrated circuit according to claim 9, wherein the further key generation device of the encryption system is identical to the key generation device of the decryption system.

13. The integrated circuit according to claim 9, wherein the further key generation device of the encryption system is same as the key generation device of the decryption system.

15. The integrated circuit according to claim 9, wherein the decryption device is configured to carry out an AES decryption algorithm and the symmetric encryption device is configured to carry out an AES encryption algorithm.

16. The integrated circuit according to claim 9, wherein the key generation device and further key generation device are each configured to carry out an AES algorithm according to a counter mode with CBC-MAC in order to generate the secret key from the key number and the unique key.

17. The integrated circuit according to claim 9, wherein the key generation device and further key generation device are each configured to implement an AES algorithm according to a mode GCM in order to generate the secret key from the key number and the unique key.