Method and Device for Managing Operation of a Computing Unit Capable of Operating with Instructions of Different Sizes

3. The method according to claim 2, wherein the processing unit is associated with a cache memory, and the rebooting of the processing unit is performed further in response to the cache memory being inactive.

5. The method according to claim 1, wherein the selection signal comprises a digital word or a header of the application program.

6. The method according to claim 1, wherein the application program is capable of being coded with instructions having two different reference sizes.

7. The method according to claim 6, wherein the two different reference sizes are respectively equal to 32 bits and 64 bits.

10. The integrated circuit according to claim 8, wherein the processing unit is further configured to execute the application program without a prior reboot, in response to the second reference size denoted by the selection signal being the same as the first reference size of the boot instructions.

12. The integrated circuit according to claim 9, further comprising a cache memory associated with the processing unit, wherein the control unit is configured to reconfigure and reboot the processing unit further in response to the cache memory being inactive.

13. The integrated circuit according to claim 8, wherein the processing unit comprises a reset pin, and wherein the control unit comprises a reset controller configured to deliver a boot signal onto the reset pin so as to boot up the processing unit with the set of boot instructions.

15. The integrated circuit according to claim 14, wherein the reboot stage comprises a logic circuit configured to receive the reboot command and input signals corresponding to the conditions, and to deliver the reboot signal onto the reset pin.

16. The integrated circuit according to claim 8, wherein the control unit is configured to deliver, to the processing unit during a reboot, a first indication representative of the second reference size denoted and a second indication representative of a storage address of the instructions of the application program.

17. The integrated circuit according to claim 16, wherein the control unit comprises a first memory one-time-writable after each reboot to store the first indication, and a second memory to store the second indication, and wherein the processing unit is configured to store the first and second indications in the respective first and second memories in response to each reboot.

18. The integrated circuit according to claim 8, further comprising an auxiliary memory configured to store a digital word representing the selection signal.

19. The integrated circuit according to claim 8, wherein the processing unit is configured to read a header of the application program indicating the selection signal.

20. The integrated circuit according to claim 8, further comprising a communications interface configured to receive the selection signal.

21. The integrated circuit according to claim 8, wherein the application program is capable of being coded with instructions having two different reference sizes.

22. The integrated circuit according to claim 21, wherein the two different reference sizes are respectively equal to 32 bits and 64 bits.