System and Method for Mapping Memory Addresses to Locations in Set-Associative Caches

2. The circuit of claim 1, wherein the circuit includes a plurality of multiplexers and wherein the selecting causes at least a portion of the plurality of modulus results to be steered among the plurality of multiplexers and combined with respective distinct portions of the input memory address.

3. The circuit of claim 1, wherein the circuit is a programmable mapper circuit, wherein the cache size is a cache size of a plurality of cache sizes supported by the programmable mapper circuit, wherein each cache size of the plurality of cache sizes is associated with a respective equation of a plurality of equations, and wherein the programmable mapper circuit is programmed based on the cache size to compute the respective equation to map the input memory address onto the cache location.

4. The circuit of claim 1, wherein the circuit is a programmable mapper circuit that is programmed based on the cache size to compute an equation of a plurality of equations, the plurality of equations configured to compute the cache location based on the input memory address.

5. The circuit of claim 4, wherein the programmable circuit includes a plurality of multiplexers and wherein the programmable mapper circuit is programmed based on the cache size to cause the plurality of multiplexers to perform the selecting in a manner that enables the programmable mapper circuit to compute the equation.

6. The circuit of claim 4, wherein the programmable mapper circuit is further configured to employ a common set of modulo operations of the plurality of modulo operations to compute the equation and wherein the common set is shared among the plurality of equations.

7. The circuit of claim 1, wherein the input memory address is (i) a memory address of a memory location in a memory or (ii) a representation of the memory address, and wherein outputting the cache location causes the cache location to be read or written in response to a read from or write to the memory address, respectively.

8. The circuit of claim 1, wherein the cache is a set-associative (SA) cache, wherein the cache size is based on a total number of sets of the SA cache and wherein the total number of sets is based on a total number of columns of banks of a plurality of banks in the SA cache, a total number of rows of banks of the plurality of banks, and a per-bank set number defining a total number of sets within each bank of the plurality of banks.

9. The circuit of claim 1, wherein the cache is a set-associative (SA) cache, wherein the cache location is identified by a row, column, and set, wherein the row and column identify a bank of a plurality of banks of the SA cache, and wherein the set identifies a set of a plurality of sets within the bank identified.

10. The circuit of claim 1, wherein the selected modulus results produced by the circuit include a first, second, and third selected modulus result, wherein the cache location is defined by a first location in a first dimension, second location in a second dimension, and third location in a third dimension, wherein the circuit includes a plurality of shifters, at least a portion of the plurality of shifters configured to perform respective bitwise left-shift operations on the first, second, and third selected modulus results used to produce the first, second, and third locations in the first, second, and third dimensions, respectively, and wherein the circuit is programmed based on the cache size to control the respective bitwise left-shift operations performed.

11. The circuit of claim 1, wherein at least a portion of the plurality of modulo operations is performed based on prime factors and wherein the cache size is decomposed into the prime factors.

13. The method of claim 12, wherein the selecting causes at least a portion of the plurality of modulus results to be steered among a plurality of multiplexers and combined with respective distinct portions of the input memory address.

14. The method of claim 12, wherein the cache size is a cache size of a plurality of cache sizes supported by a programmable mapper circuit, wherein each cache size of the plurality of cache sizes is associated with a respective equation of a plurality of equations, and wherein the method further comprises programming the programmable mapper circuit based on the cache size to compute the respective equation to map the input memory address onto the cache location.

15. The method of claim 12, further comprising programming a programmable mapper circuit based on the cache size to compute an equation of a plurality of equations, the plurality of equations configured to compute the cache location based on the input memory address.

16. The method of claim 15, wherein the programmable mapper circuit includes a plurality of multiplexers and wherein the programming causes the plurality of multiplexers to perform the selecting in a manner that enables the programmable mapper circuit to compute the equation.

17. The method of claim 15, wherein the programming further causes the programmable mapper circuit to employ a common set of modulo operations of the plurality of modulo operations to compute the equation and wherein the common set is shared among the plurality of equations.

18. The method of claim 12, wherein the input memory address is (i) a memory address of a memory location in a memory or (ii) a representation of the memory address, and wherein outputting the cache location causes the cache location to be read or written in response to a read from or write to the memory address, respectively.

19. The method of claim 12, wherein the cache is a set-associative (SA) cache, wherein the cache size is based on a total number of sets of the SA cache and wherein the total number of sets is based on a total number of columns of banks of a plurality of banks in the SA cache, a total number of rows of banks of the plurality of banks, and a per-bank set number defining a total number of sets within each bank of the plurality of banks.

20. The method of claim 12, wherein the cache is a set-associative (SA) cache, wherein the outputting includes outputting a row, column, and set that identify the cache location, wherein the row and column identify a bank of a plurality of banks of the SA cache, and wherein the set identifies a set of a plurality of sets within the bank identified.

21. The method of claim 12, wherein the selected modulus results include first, second, and third selected modulus results, wherein the cache location is defined by a first location in a first dimension, second location in a second dimension, and third location in a third dimension, wherein the method further comprises performing respective bitwise left-shift operations on the first, second, and third selected modulus results to produce the first, second, and third locations, respectively, in the first, second, and third dimensions, respectively, and controlling, based on the cache size, the respective bitwise left-shift operations performed.

22. The method of claim 12, wherein the cache is a set-associative (SA) cache, wherein the cache size is a cache size among a plurality of cache sizes of SA caches and wherein at least a portion of the plurality of modulo operations performed are determined based on prime factors, the cache size decomposed into the prime factors.