Memory System and Operating Method Thereof

2. The operating method of claim 1, wherein the first memory chip and the second memory chip are connected to different channels.

4. The operating method of claim 1, wherein the first memory chip and the second memory chip are connected to a same channel.

6. The operating method of claim 1, wherein the determining whether the first memory chip and the second memory chip are performing the erase operation or the program operation for the second data comprises determining whether the first memory chip and the second memory chip are performing the erase operation or the program operation for the second data based on a busy flag stored in a controller controlling the first memory chip and the second memory chip.

8. The operating method of claim 7, wherein the reading of the first data from the second memory chip is based on the first physical address of the mapping table.

11. The operating method of claim 10, wherein the programming of the first data in each of the plurality of memory chips comprises programming the first data in a first memory chip and a second memory chip connected to different channels.

13. The operating method of claim 10, wherein the programming of the first data in each of the plurality of memory chips comprises programming the first data in a first memory chip and a second memory chip connected to a same channel.

15. The operating method of claim 10, further comprising generating a busy flag when at least one of the plurality of memory chips is performing the erase operation or the program operation for data different from the first data.

17. The operating method of claim 16, wherein the reading of the first data from the one memory chip of the plurality of memory chips is based on the first physical address in the mapping table.