Data processing method for controlling write speed of memory device to avoid significant write delay and data storage device utilizing the same

4. The data processing method as claimed in claim 3, wherein the target write speed determined in the first operation period and the re-determined target write speed re-determined in the second operation period are different.

5. The data processing method as claimed in claim 3, wherein the target garbage collection speed determined in the first operation period and the re-determined target garbage collection speed re-determined in the second operation period are different.

6. The data processing method as claimed in claim 1, wherein the balance speed is related to a read speed of the memory device.

7. The data processing method as claimed in claim 1, wherein the balance speed is related to a write speed of the memory device.

9. The memory controller as claimed in claim 8, wherein the microprocessor is further configured to configure a size of the first cache memory and a size of the second cache memory utilized in the first operation period according to the target write speed and the target garbage collection speed, wherein the first cache memory is utilized for buffering write data received from the host device to assist the microprocessor in executing the one or more write commands, and the second cache memory is utilized for assisting the microprocessor in performing the at least one garbage collection operation.

10. The memory controller as claimed in claim 8, wherein the microprocessor is further configured to obtain the number of spare blocks of the flash memory device corresponding to the second operation period, re-determine the write speed compensation value according to the number of spare blocks, re-determine the target write speed according to the re-determined write speed compensation value and the balance speed, and re-determine the target garbage collection speed according to the re-determined target write speed, and wherein the microprocessor is further configured to process one or more write commands received from the host device in the second operation period according to the re-determined target write speed and perform the at least one garbage collection operation in the second operation period according to the re-determined target garbage collection speed.

11. The memory controller as claimed in claim 10, wherein the target write speed determined in the first operation period and the target write speed re-determined in the second operation period are different.

12. The memory controller as claimed in claim 10, wherein the target garbage collection speed determined in the first operation period and the target garbage collection speed re-determined in the second operation period are different.

13. The memory controller as claimed in claim 8, wherein the balance speed is related to a read speed of the flash memory device.

14. The memory controller as claimed in claim 8, wherein the balance speed is related to a write speed of the flash memory device.