Path Discrimination

2. The apparatus as claimed in claim 1 wherein the at least one memory comprises stored instructions that, when executed by the at least one processor, cause the apparatus to provide an output identifying each of the candidate line of sight paths.

4. The apparatus as claimed in claim 1 wherein there are multiple candidate line of sight paths and wherein the at least one memory comprises stored instructions that, when executed by the at least one processor, cause the apparatus to rank the multiple candidate line of sight paths by received power.

5. The apparatus as claimed in claim 4 wherein the at least one memory comprises stored instructions that, when executed by the at least one processor, cause the apparatus to identify the path with the highest identified received power as a shortest path and to provide an output identifying said shortest path.

6. The apparatus as claimed in claim 1 wherein the at least one memory comprises stored instructions that, when executed by the at least one processor, cause the apparatus to perform calculating one or both of a corrected delay or a delay correction factor.

7. The apparatus as claimed in claim 6, wherein calculating the delay correction factor comprises determining a relative time difference between a communication path based on a non-line of sight path and a shortest path.

8. The apparatus as claimed in claim 1 wherein the at least one memory comprises stored instructions that, when executed by the at least one processor, cause the apparatus to determine a beam index of one or both of a shortest path or each candidate line of sight path.

11. The method as claimed in claim 10 further comprising: providing an output identifying each of the candidate line of sight paths.

13. The method as claimed in claim 10 further comprising: ranking one or more of the candidate line of sight paths by received power.

14. The method as claimed in claim 13 further comprising: identifying the path with the highest identified received power as a shortest path and providing an output identifying said shortest path.

15. The method as claimed in claim 10 further comprising: calculating one or both of a corrected delay or a delay correction factor.

17. The apparatus as claimed in claim 1, wherein each synchronisation symbol block starts at a specific one of a plurality of symbols in a subframe.

18. The apparatus as claims in claim 17, wherein each synchronisation symbol block and corresponding beam is sent in a different direction.