Pixel Structure, Array Substrate and Display Panel

2. The pixel structure of claim 1, wherein the first pixel unit and the second pixel unit are set on a same side of the first data line.

3. The pixel structure of claim 2, wherein the first thin film transistor and the second thin film transistor are respectively set on two sides of the first direction that the first pixel electrode is along and are symmetrically arranged.

4. The pixel structure of claim 1, wherein shapes of the first pixel electrode and the second pixel electrode are the same and the first pixel electrode and the second pixel electrode are set symmetrically.

6. The pixel structure of claim 1, wherein two terminals of the first gate line connected to the first gate electrode are set in a staggered manner in the first direction; and two terminals of the second gate line connected to the second gate electrode are set in a staggered manner in the first direction.

7. The pixel structure of claim 1, wherein the first source electrode and the first drain electrode are both extendedly arranged along the second direction; and the second source electrode and the second drain electrode are both extendedly arranged the second direction.

8. The pixel structure of claim 1, wherein line impedances of the first connecting trace and the second connecting trace are equivalent.

9. The pixel structure of claim 1, wherein a storage capacitance formed by the first connecting trace is equal to a storage capacitance formed by the second connecting trace.

10. The pixel structure of claim 9, wherein the pixel structure further comprises a common electrode; the storage capacitance of the first pixel unit is formed by the common electrode and the first pixel electrode as well as the common electrode and the first connecting trace; the storage capacitance of the second pixel unit is formed by the common electrode and the second pixel electrode as well as the common electrode and the second connecting trace.

11. The pixel structure of claim 1, wherein the pixel structure comprises a plurality of first data lines, and the plurality of first data lines are arranged in the second direction; the pixel structure comprises a plurality of first gate lines and a plurality of second gate lines, the plurality of first gate lines and the plurality of second gate lines are arranged along the first direction; the pixel structure comprises a plurality of first pixel units and a plurality of second pixel units, the plurality of first pixel units and the plurality of second pixel units are arranged in an array; wherein, a pixel group is formed by one first pixel unit and one second pixel unit which are adjacent with each others in the second direction and are connecting to a same first data line, two pixel groups adjacent in the first direction, are respectively connected to two adjacent first data lines.

12. The pixel structure of claim 11, wherein projections of the two adjacent pixel groups in the first direction are arranged embeddedly.

14. The pixel structure of claim 1, wherein the first pixel unit and the second pixel unit are respectively located at two sides of the first data line.

15. The pixel structure of claim 14, wherein a third pixel unit is set between the second pixel unit and the first data line, the third pixel unit is connected to a second data line that is extended along the first direction and is adjacent to the first data line; a side of the second data line that is far from the third pixel line is connected to the fourth pixel unit; the third pixel unit is connected to the first gate line, the fourth pixel unit is connected to the second gate line.

17. The array substrate of claim 16, further comprising a color resistance layer set on the second insulating layer, wherein the transparent line section is set on the color resistance layer; the via connecting section is set to be crossing through the color resistance layer.

18. The array substrate of claim 16, wherein the first connecting trace and the second connecting trace is set to match the capacitance of the first pixel unit with the capacitance of the second pixel unit through a matching setting of transparent line sections.

19. A display panel comprising a pixel structure of claim 1.

20. A display panel comprising an array substrate of claim 16 and a color film substrate set oppositely to the array substrate.