Network Device

2. The network device of claim 1, wherein the processor executes a MOD function computation on the calendar time TOD and the bit number N to obtain the remainder R.

3. The network device of claim 1, wherein the processor executes a division computation on the calendar time TOD and the bit number N to obtain the remainder R and a quotient Q.

4. The network device of claim 1, wherein the first port is set as a normal mode, and the second port is set as a transparent mode; wherein the processor writes the calendar time TOD into the timestamp field and writes a complement (−R) of the remainder (R) into the correction field.

5. The network device of claim 1, wherein the first port is set as a normal mode, and the second port is set as a transparent mode; wherein the processor computes a difference between a first remainder R1 and the calendar time TOD and writes the difference into the timestamp field, and the processor writes 0 or a null value into the correction field.

7. The network device of claim 6, wherein the processor adds the corresponding quotient QREQ with 1 when the delay request packet input time TiREQ is larger than the corresponding remainder RREQ.

10. The network device of claim 9, wherein the processor executes a MOD function computation on the second calendar time TOD2 and the bit number N to obtain the second remainder R2.

11. The network device of claim 9, wherein the processor executes a division computation on the second calendar time TOD2 and the bit number N to obtain the second remainder R2.

12. The network device of claim 9, wherein the processor computes a summation of the second calendar time TOD2, the second remainder R2, and a difference which subtracts the first remainder R1 from the first chip receiving time Ti1 and writes the summation into the timestamp field of the second synchronization packet, and a complement (−R2) of the second remainder R2 is written into the correction field of the second synchronization packet.

13. The network device of claim 8, wherein the processor computes a summation of the second calendar time TOD2 and a difference value which subtracts the first remainder R1 from the first chip receiving time Ti1 and writes the summation into the timestamp field of the second synchronization packet, and the processor writes 0 or a null value into the correction field.

15. The network device of claim 14, wherein the processor adds 1 to the corresponding quotient QREQ when the delay request packet input time TiREQ is larger than the corresponding remainder RREQ.