System, Apparatus and Method for Responsive Autonomous Hardware Performance State Control of a Processor

2. The processor of claim 1, wherein the target utilization value is dependent on the energy performance preference hint.

3. The processor of claim 1, wherein the energy performance preference hint is to be generated in the operating system and have a value to indicate a relative preference between performance and energy conservation.

4. The processor of claim 1, wherein in response to the update to the energy performance preference hint, the hardware performance state controller is to update the performance state of the first core from a first performance state to a second performance state in a single iteration.

5. The processor of claim 1, wherein the hardware performance state controller is to access a table using the energy performance preference hint to determine the target utilization value.

8. The processor of claim 1, further comprising a graphics engine coupled to the first core.

9. The processor of claim 8, further comprising a cache memory coupled to the graphics engine.

10. The processor of claim 1, wherein the hardware performance state controller is to update the performance state of the first core within 1 millisecond of the update to the energy performance preference hint.

11. The processor of claim 1, wherein the power controller is to control the power consumption of the processor further based at least in part on Amdahl's law.

13. The method of claim 12, further comprising in response to the update to the energy performance preference hint, updating the performance state of the first core from a first performance state to a second performance state in a single iteration.

14. The method of claim 12, further comprising accessing a table using the energy performance preference hint to determine the target utilization value.

16. The non-transitory machine-readable medium of claim 15, wherein the method further comprises in response to the update to the energy performance preference hint, updating the performance state of the first core from a first performance state to a second performance state in a single iteration.