11675700

Cache Coherence Shared State Suppression

PublishedJune 13, 2023
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
7 claims

Legal claims defining the scope of protection, as filed with the USPTO.

4

4. The device of claim 1, wherein the second cache coherence state is an invalid state.

5

5. The device of claim 1, wherein the second cache coherence state is an exclusive state.

8

8. The device of claim 1, wherein the first request includes a snoop command.

9

9. The device of claim 1, wherein the first request includes a cache management operation.

14

14. The system of claim 12, wherein the second cache coherence state is either an invalid state or an exclusive state.

18

18. The method of claim 15, wherein the second cache coherence state is an invalid state.

19

19. The method of claim 15, wherein the second cache coherence state is an exclusive state.

Patent Metadata

Filing Date

Unknown

Publication Date

June 13, 2023

Inventors

Abhijeet Ashok CHACHAD
David Matthew THOMPSON
Timothy David ANDERSON
Kai CHIRCA

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Cite as: Patentable. “CACHE COHERENCE SHARED STATE SUPPRESSION” (11675700). https://patentable.app/patents/11675700

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CACHE COHERENCE SHARED STATE SUPPRESSION — Abhijeet Ashok CHACHAD | Patentable