3d Stack of Accelerator Die and Multi-Core Processor Die

2. The apparatus of claim 1 comprising a first passive silicon adjacent to the accelerator die and over a first set of processor cores of the plurality of processor cores.

3. The apparatus of claim 2 comprising a second passive silicon adjacent to the accelerator die and over a second set of processor cores of the plurality of processor cores.

4. The apparatus of claim 3, wherein the first set of processor cores and the second set of processor cores are on either side of the memory of the processor die.

5. The apparatus of claim 3, wherein the first passive silicon or the second passive silicon comprises passive components.

6. The apparatus of claim 5, wherein the passive components include one or more of: inductors, capacitors, interconnect, or power supply components for the plurality of processor cores.

7. The apparatus of claim 1, wherein the accelerator die consumes more power than the processor die.

8. The apparatus of claim 1 comprising a heat sink to manage thermals of the processor die and the accelerator die.

9. The apparatus of claim 1, wherein the memory comprises cache.

10. The apparatus of claim 1, wherein the accelerator die includes a first interconnect fabric, wherein the processor die includes a second interconnect fabric, and wherein the first interconnect fabric is coupled to the second interconnect fabric.

11. The apparatus of claim 10, wherein the first interconnect fabric or the second interconnect fabric includes one of: network on chip, mesh fabric, or a ring fabric.

12. The apparatus of claim 10, wherein the first interconnect fabric is coupled to the second interconnect fabric via copper-to-copper bonding.

13. The apparatus of claim 1, wherein the accelerator die includes ferroelectric logic or paraelectric logic.

14. The apparatus of claim 13, wherein the ferroelectric logic or the paraelectric logic include a majority gate, a minority gate, or a threshold gate.

15. The apparatus of claim 13, wherein the ferroelectric logic or the paraelectric logic includes non-linear polar material which includes one of: ferroelectric material, paraelectric material, or non-linear dielectric.

17. The apparatus of claim 15, wherein the paraelectric material includes: SrTiO3, Ba(x)Sr(y)TiO3 where x is −0.05 and y is 0.95, HfZrO2, Hf—Si—O, La-substituted PbTiO3, or PMN-PT based relaxor ferroelectrics.