Driving Circuit and Display Panel

9. The driving circuit of claim 8, wherein a timing of the fourth clock signal is identical to a timing of the third clock signal, a voltage level of the fourth clock signal is higher than a voltage level of the third clock signal; the timing of the third clock signal and a timing of the second clock signal are staggered; the timing of the second clock signal and a timing of the first clock signal are staggered; the timing of the third clock signal and the timing of the first clock signal are staggered; and the voltage level of the third clock signal is identical to a voltage level of the second clock signal and a voltage level of the first clock signal.

10. The driving circuit of claim 1, wherein the stage signal is a driving signal transferred to low temperature poly-silicon (LTPS) TFTs in a non-display area of a display panel, the gate driving signal is a driving signal transferred to oxide TFTs in a display area of the display panel.

19. The display panel of claim 18, wherein a timing of the fourth clock signal is identical to a timing of the third clock signal, a voltage level of the fourth clock signal is higher than a voltage level of the third clock signal; the timing of the third clock signal and a timing of the second clock signal are staggered; the timing of the second clock signal and a timing of the first clock signal are staggered; the timing of the third clock signal and the timing of the first clock signal are staggered; and the voltage level of the third clock signal is identical to a voltage level of the second clock signal and a voltage level of the first clock signal.

20. The display panel of claim 11, wherein the stage signal is a driving signal transferred to low temperature poly-silicon (LTPS) TFTs in a non-display area of a display panel, the gate driving signal is a driving signal transferred to oxide TFTs in a display area of the display panel.