Fractional Frequency Divider and Flash Memory Controller

2. The fractional frequency divider of claim 1, wherein a number of the plurality of counter values is the same as a number of the at least a portion of the registers; and if the register corresponding to the counter value received by the control signal generator has a first value, the control signal generator generates the control signal having a first logical value; and if the register corresponding to the counter value received by the control signal generator has a second value, the control signal generator generates the control signal having a second logical value.

3. The fractional frequency divider of claim 2, wherein when the control signal has the first logical value, the clock gating circuit masks the input clock signal to make the output clock signal not have an enabling period; and when the control signal has the second logical value, the clock gating circuit does not mask the input clock signal so that the output clock signal is generated by the input clock signal.

4. The fractional frequency divider of claim 3, wherein the counter generates only one counter value to the control signal generator corresponding to one cycle of the input clock signal; and for each cycle of the input clock signal, when the control signal has the first logical value, the clock gating circuit masks the input clock signal to make the output clock signal not have the enabling period within the cycle; and when the control signal has the second logical value, the clock gating circuit does not mask the input clock signal so that the output clock signal is the same as the input clock signal within the cycle.