Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein the first register and the second register correspond with each other, and wherein bits stored in the first register and bits stored in the second register represent an operand, of the operands, of the first size.
3. The method of claim 2, wherein the first register stores a plurality of bits of a different significance than a plurality of bits stored in the second register.
5. The method of claim 1, wherein said selecting one of the first register and the second register comprises selecting the first register in response to receiving a first non-null select value of the select values, and not selecting the second register in absence of receiving a second non-null select value of the select values.
8. The method of claim 6, wherein said performing operations of the first size comprises reading bits of a plurality of registers of the second array in a first clock cycle prior to reading bits of a plurality of registers of the first array in a second clock cycle.
10. The method of claim 1, further comprising returning a result of the first size, wherein the result is stored partially in a first destination register in the first array and partially in a second destination register in the second array.
11. The method of claim 1, further comprising returning a result of the second size stored in a destination register in one of the first array and the second array.
13. The system of claim 12, wherein the first register and the second register correspond to each other, and wherein bits stored in the first register and bits stored in the second register represent an operand, of the operands, of the first size.
14. The system of claim 13, wherein the first register stores a plurality of bits of a different significance than a plurality of bits stored in the second register.
15. The system of claim 12, wherein the multiplexer is configured to select the first register in response to receiving a first non-null select value of the select values, and to select the second register in response to receiving a second non-null select value of the select values.
16. The system of claim 12, wherein the multiplexer is configured to select the first register in response to receiving a first non-null select value of the select values, and to not select the second register in absence of receiving a second non-null select value of the select values.
17. The system of claim 12, wherein the functional unit is configured to perform a first operation, of the operations, on data of the first register and to perform a second operation, of the operations, on data of the second register, wherein the first operation and the second operation are related to a same instruction.
18. The system of claim 17, wherein the functional unit is further configured to read bits of a first operand, of the operands, in the second register in a same clock cycle as bits of a second operand, of the operands, in the first register based on an operation, of the operations, being based on at least one of a pairwise instruction and an across-vector instruction, and to read bits of the first operand in a third register, of the second array, in a next clock cycle following the same clock cycle as bits of the second operand in a fourth register, of the first array, when the same instruction is a pairwise instruction.
19. The system of claim 17, wherein the functional unit is further configured to read bits of a plurality of registers of the second array in a first clock cycle prior to reading bits of a plurality of registers of the first array in a second clock cycle.
21. The system of claim 12, configured to return a result of the first size, wherein the result is stored partially in a first destination register in the first array and partially in a second destination register in the second array.
22. The system of claim 12, configured to return a result of the second size stored in a destination register in one of the first array and the second array.
24. The non-transitory computer-readable medium of claim 23, wherein the first register and the second register correspond to each other, and wherein bits stored in the first register and bits stored in the second register represent an operand, of the operands, of the first size.
25. The non-transitory computer-readable medium of claim 24, wherein the first register and the second register correspond with each other, and wherein the first register stores a plurality of bits of a different significance than a plurality of bits stored in the second register.
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July 25, 2023
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