Legal claims defining the scope of protection, as filed with the USPTO.
2. The apparatus of claim 1, wherein the weighted summation further comprises a two-UI precursor signal component.
3. The apparatus of claim 1, wherein each of the post-cursor signal component, the main signal component, and the precursor signal component are weighted via an assignment of a corresponding number of output driver circuits of the set of output driver circuits.
4. The apparatus of claim 1, wherein the set of output driver circuits comprises at least forty output driver circuits.
5. The apparatus of claim 1, wherein the weighted summation is generated at a common output node connected to the set of output driver circuits, each output driver circuit connected to the common output node via a respective resistive element.
6. The apparatus of claim 5, wherein each respective resistive element has an impedance value larger than a characteristic impedance of the respective wire of the multi-wire bus, and wherein a collective output impedance of the set of output driver circuits matches the characteristic impedance of the respective wire of the multi-wire bus.
7. The apparatus of claim 6, wherein the set of output driver circuits comprises one or more disabled output driver circuits.
8. The apparatus of claim 1, wherein the plurality of phase comparators are further configured to independently adjust output timing of each of the post-cursor signal component, the main signal component, and the precursor signal component.
9. The apparatus of claim 1, wherein each output driver is configured to generate at least four possible signal values on the respective wire of the multi-wire bus.
10. The apparatus of claim 9, wherein each output tap of the plurality of output taps is configured to output at least two control bits to the selected output driver circuit.
12. The method of claim 11, wherein the weighted summation further comprises a two-UI precursor signal component.
13. The method of claim 11, wherein each of the post-cursor signal component, the main signal component, and the precursor signal component are weighted via an assignment of a corresponding number of output driver circuits of the set of output driver circuits.
14. The method of claim 11, wherein each respective set of output driver circuits comprises at least forty output driver circuits.
15. The method of claim 11, wherein the weighted summation is generated at a common output node connected to the set of output driver circuits, each output driver circuit connected to the common output node via a respective resistive element.
16. The method of claim 15, wherein each respective resistive element has an impedance value larger than a characteristic impedance of the respective wire of the multi-wire bus, and wherein a collective output impedance of the set of output driver circuits matches the characteristic impedance of the respective wire of the multi-wire bus.
17. The method of claim 16, wherein one or more output driver circuits in each respective set of output driver circuits are disabled.
18. The method of claim 11, further comprising adjusting individual output timing of each of the post-cursor signal component, the main signal component, and the precursor signal component.
19. The method of claim 11, wherein each of the post-cursor signal component, the main signal component, and the precursor signal component have one of at least four possible signal values.
20. The method of claim 19, wherein each output tap of the plurality of output taps of the data buffer comprises at least two control bits.
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August 1, 2023
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