Memory System with Write Modes Based on an Internal State of a Memory Controller

4. The memory system of claim 3, wherein the second management unit is determined based on an access unit of the host to the memory system.

8. The memory system of claim 1, wherein the controller is further configured to manage the physical address specified by the controller as the write destination of the data in the second memory area, by a ring buffer method.

11. The memory system of claim 1, wherein when writing the data designated in the write command to the first memory area, where it is determined a Read Modify Write process is executed, the controller is further configured to determine the second method as the write method.

12. The memory system of claim 1, wherein when a number of times of generating write commands within a period is smaller than a predetermined value, the controller is further configured to determine the first method as the write method.

13. The memory system of claim 1, wherein when the first memory area where the data designated in the write command is written is in a busy state, the controller is further configured to determine the second method as the write method.

14. The memory system of claim 1, wherein when a frequency of the logical address in the write command is higher than a predetermined value, the controller is further configured to determine the second method as the write method.

18. The memory system of claim 1, wherein the controller comprises an ECC circuit generating a parity for error correction by packing a plurality of data in a second management unit in which a correspondence between the logical address and the physical address in the second memory area is managed.

19. The memory system of claim 1, wherein the controller comprises an ECC circuit generating a parity for error correction for each data in a second management unit in which a correspondence between the logical address and the physical address in the second memory area is managed.

20. The memory system of claim 1, wherein a correspondence between the logical address and the physical address in the second memory area is managed by a set associative method.

21. The memory system of claim 1, wherein a correspondence between the logical address and the physical address in the second memory area is managed by a list method.

23. The memory system of claim 20, wherein the correspondence between the logical address and the physical address in the second memory area is managed with a hash value calculated with the logical address.

24. The memory system of claim 20, wherein when a read command in which the logical address for accessing the data to be read from the non-volatile memory is designated is received from the host, the controller is further configured to acquire a physical address corresponding to the logical address designated in the read command by referring to second address translation data for managing the correspondence between the logical address and the physical address in the second memory area.

25. The memory system of claim 24, wherein when the physical address corresponding to the logical address designated in the read command is unable to be acquired by referring to the second address translation data, the controller is configured to acquire the physical address corresponding to the logical address designated in the read command by referring to first address translation data for managing a correspondence between the logical address and the physical address in the first memory area.

27. The memory system of claim 1, wherein the controller is further configured to write back the data written to the second memory area, to the first memory area.

28. The memory system of claim 27, wherein the controller is further configured to write back valid data, of the data written to the second memory area, to the first memory area.

30. The memory system of claim 27, wherein the controller is further configured to write back the data written to the second memory area to the first memory area when a patrol and refresh process is executed for the first memory area.

31. The memory system of claim 27, wherein when a read command for reading the data from the non-volatile memory is received from the host, the controller is further configured to write back the data written to the second memory area to the first memory area.

32. The memory system of claim 27, wherein the controller is further configured to write back the data written to the second memory area, to the first memory area, when a wear leveling process of changing a correspondence between the logical address and the physical address in the second memory area is executed based on a number of times of writing the data to the physical address in the second memory area.

33. The memory system of claim 27, wherein when the memory system is rebooted, the controller is further configured to write back the data written to the second memory area to the first memory area.

34. The memory system of claim 1, wherein when a number of times of generating read or write commands within a predetermined period is smaller than a predetermined value, the controller is further configured to write back the data written to the second memory area to the first memory area.

36. The memory system of claim 1, wherein when updating second address translation data for managing a correspondence between the logical address used when the host accesses the memory system and the physical address in the second memory area, the controller is further configured to generate an update log on the updating and write the update log to the non-volatile memory.

37. The memory system of claim 36, wherein the controller is further configured to set a buffer area of the update log for each part of the second address translation data in the non-volatile memory, and write the update log generated when a part of the second address translation data is updated, to the buffer area corresponding to the part of the second address translation data.

38. The memory system of claim 1, wherein the controller is further configured to write to the non-volatile memory at least an updated part of second address translation data for managing a correspondence between the logical address used when the host accesses the memory system and the physical address in the second memory area.

39. The memory system of claim 38, wherein after the updated part of the second address translation data is written to the non-volatile memory, the controller is further configured to discard an update log on the updated part written to the non-volatile memory.

40. The memory system of claim 1, wherein when the memory system is rebooted, the controller is further configured to read from the non-volatile memory second address translation data for managing a correspondence between the logical address used when the host accesses the memory system and the physical address in the second memory area, and an update log generated when a part of the second address translation data is updated, and update the second address translation data, based on the update log.

42. The memory system of claim 1, wherein a size of the second memory area is capable of being designated by an outside of the memory system.

43. The memory system of claim 42, wherein the size of the second memory area capable of being designated from the outside is designated for each partition or namespace.