Memory Region Allocation to a Software Program

2. The processor of claim 1, wherein the decoder is also to decode a third instruction, the third instruction to specify an encrypted first address associated with the data object, the processor further comprising decryption circuitry to decrypt the encrypted first address to generate a decrypted address and a decrypted memory tag.

3. The processor of claim 1, wherein the first address is a virtual address and the second address is a physical address.

4. The processor of claim 1, wherein the memory controller is also to prevent loading a cache line corresponding to the memory location until the comparator has detected the match between the first memory tag and the second memory tag.

5. The processor of claim 1, wherein the memory controller is also to, in response to the comparator detecting a mismatch between the first memory tag and the second memory tag, load data not indicative of the data object into a cache line corresponding to the memory location.

6. The processor of claim 1, further comprising pointer security circuitry to provide the first memory tag.

7. The processor of claim 1, wherein the encryption circuitry is also to cryptographically secure the data object at least partially based on the first memory tag.

8. The processor of claim 1, wherein the first memory tag includes an identification tag to identify a type, a function, a memory location, or a use for the data object.

9. The processor of claim 7, wherein the encryption circuitry uses a least a portion of the memory tag to at least partially define a tweak input to an encryption algorithm.

10. The processor of claim 7, wherein the first memory tag includes an encryption tag, wherein the encryption circuitry is to use the encryption tag to identify one of a plurality of encryption keys.

11. The processor of claim 1, wherein the first memory tag includes a small object tag to indicate whether a cache line associated with the memory location is to include a plurality of data objects.

12. The processor of claim 11, wherein the small object tag is to enable sub-cacheline granularity of memory tagging.

13. The processor of claim 1, further comprising integrity check circuitry to generate an integrity check value at least partially based on the first address and an encrypted value of the data object.

14. The processor of claim 13, further comprising pointer security circuitry to detect tampering with the first address at least partially based on the integrity check values.

17. The method of claim 15, wherein the first address is a virtual address and the second address is a physical address.

18. The method of claim 15, further comprising preventing loading a cache line corresponding to the memory location until the match is detected.

19. The method of claim 15, further comprising loading, in response to detecting a mismatch between the first memory tag and the second memory tag, data not indicative of the data object into a cache line corresponding to the memory location.

20. The method of claim 15, further comprising decrypting an encrypted address to provide the first address and the first memory tag.